src/cdef_tmpl.c

@@ -310,6 +310,8 @@ static int cdef_find_dir_c(const pixel *img, const ptrdiff_t stride,
 #include "src/ppc/cdef.h"
 #elif ARCH_X86
 #include "src/x86/cdef.h"
+#elif ARCH_LOONGARCH64
+#include "src/loongarch/cdef.h"
 #endif
 #endif
 
@@ -326,6 +328,8 @@ COLD void bitfn(dav1d_cdef_dsp_init)(Dav1dCdefDSPContext *const c) {
     cdef_dsp_init_ppc(c);
 #elif ARCH_X86
     cdef_dsp_init_x86(c);
+#elif ARCH_LOONGARCH64
+    cdef_dsp_init_loongarch(c);
 #endif
 #endif
 }

src/ipred_tmpl.c

@@ -734,6 +734,8 @@ static void pal_pred_c(pixel *dst, const ptrdiff_t stride,
 #include "src/arm/ipred.h"
 #elif ARCH_X86
 #include "src/x86/ipred.h"
+#elif ARCH_LOONGARCH64
+#include "src/loongarch/ipred.h"
 #endif
 #endif
 
@@ -769,6 +771,8 @@ COLD void bitfn(dav1d_intra_pred_dsp_init)(Dav1dIntraPredDSPContext *const c) {
     intra_pred_dsp_init_arm(c);
 #elif ARCH_X86
     intra_pred_dsp_init_x86(c);
+#elif ARCH_LOONGARCH64
+    intra_pred_dsp_init_loongarch(c);
 #endif
 #endif
 }

src/loongarch/cdef.h

+/*
+ * Copyright © 2024, VideoLAN and dav1d authors
+ * Copyright © 2024, Loongson Technology Corporation Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DAV1D_SRC_LOONGARCH_CDEF_H
+#define DAV1D_SRC_LOONGARCH_CDEF_H
+
+#include "config.h"
+#include "src/cdef.h"
+#include "src/cpu.h"
+
+decl_cdef_dir_fn(BF(dav1d_cdef_find_dir, lsx));
+decl_cdef_fn(BF(dav1d_cdef_filter_block_4x4, lsx));
+decl_cdef_fn(BF(dav1d_cdef_filter_block_4x8, lsx));
+decl_cdef_fn(BF(dav1d_cdef_filter_block_8x8, lsx));
+
+static ALWAYS_INLINE void cdef_dsp_init_loongarch(Dav1dCdefDSPContext *const c) {
+    const unsigned flags = dav1d_get_cpu_flags();
+
+    if (!(flags & DAV1D_LOONGARCH_CPU_FLAG_LSX)) return;
+
+#if BITDEPTH == 8
+    c->dir = BF(dav1d_cdef_find_dir, lsx);
+    c->fb[0] = BF(dav1d_cdef_filter_block_8x8, lsx);
+    c->fb[1] = BF(dav1d_cdef_filter_block_4x8, lsx);
+    c->fb[2] = BF(dav1d_cdef_filter_block_4x4, lsx);
+#endif
+}
+
+#endif /* DAV1D_SRC_LOONGARCH_CDEF_H */

src/loongarch/ipred.h

+/*
+ * Copyright © 2024, VideoLAN and dav1d authors
+ * Copyright © 2024, Loongson Technology Corporation Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DAV1D_SRC_LOONGARCH_IPRED_H
+#define DAV1D_SRC_LOONGARCH_IPRED_H
+
+#include "config.h"
+#include "src/ipred.h"
+#include "src/cpu.h"
+#include "src/tables.h"
+
+#define MULTIPLIER_1x2 0x5556
+#define MULTIPLIER_1x4 0x3334
+#define BASE_SHIFT 16
+
+#define init_fn(type0, type1, name, suffix) \
+    c->type0[type1] = BF(dav1d_##name, suffix)
+
+#define init_angular_ipred_fn(type, name, suffix) \
+    init_fn(intra_pred, type, name, suffix)
+#define init_cfl_pred_fn(type, name, suffix) \
+    init_fn(cfl_pred, type, name, suffix)
+
+decl_angular_ipred_fn(BF(dav1d_ipred_dc, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_dc_128, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_dc_top, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_dc_left, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_h, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_v, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_paeth, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_smooth, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_smooth_v, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_smooth_h, lsx));
+decl_angular_ipred_fn(BF(dav1d_ipred_filter, lsx));
+
+decl_cfl_pred_fn(BF(dav1d_ipred_cfl, lsx));
+decl_cfl_pred_fn(BF(dav1d_ipred_cfl_128, lsx));
+decl_cfl_pred_fn(BF(dav1d_ipred_cfl_top, lsx));
+decl_cfl_pred_fn(BF(dav1d_ipred_cfl_left, lsx));
+
+decl_pal_pred_fn(BF(dav1d_pal_pred, lsx));
+
+static ALWAYS_INLINE void intra_pred_dsp_init_loongarch(Dav1dIntraPredDSPContext *const c) {
+    const unsigned flags = dav1d_get_cpu_flags();
+
+    if (!(flags & DAV1D_LOONGARCH_CPU_FLAG_LSX)) return;
+
+#if BITDEPTH == 8
+    init_angular_ipred_fn(DC_PRED,       ipred_dc,       lsx);
+    init_angular_ipred_fn(DC_128_PRED,   ipred_dc_128,   lsx);
+    init_angular_ipred_fn(TOP_DC_PRED,   ipred_dc_top,   lsx);
+    init_angular_ipred_fn(LEFT_DC_PRED,  ipred_dc_left,  lsx);
+    init_angular_ipred_fn(HOR_PRED,      ipred_h,        lsx);
+    init_angular_ipred_fn(VERT_PRED,     ipred_v,        lsx);
+    init_angular_ipred_fn(PAETH_PRED,    ipred_paeth,    lsx);
+    init_angular_ipred_fn(SMOOTH_PRED,   ipred_smooth,   lsx);
+    init_angular_ipred_fn(SMOOTH_V_PRED, ipred_smooth_v, lsx);
+    init_angular_ipred_fn(SMOOTH_H_PRED, ipred_smooth_h, lsx);
+    init_angular_ipred_fn(FILTER_PRED,   ipred_filter,   lsx);
+
+    init_cfl_pred_fn(DC_PRED,      ipred_cfl,      lsx);
+    init_cfl_pred_fn(DC_128_PRED,  ipred_cfl_128,  lsx);
+    init_cfl_pred_fn(TOP_DC_PRED,  ipred_cfl_top,  lsx);
+    init_cfl_pred_fn(LEFT_DC_PRED, ipred_cfl_left, lsx);
+
+    c->pal_pred = BF(dav1d_pal_pred, lsx);
+#endif
+}
+
+#endif /* DAV1D_SRC_LOONGARCH_IPRED_H */

src/loongarch/itx.h

@@ -31,67 +31,18 @@
 #include "src/cpu.h"
 #include "src/itx.h"
 
-decl_itx_fn(BF(dav1d_inv_txfm_add_wht_wht_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_flipadst_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_adst_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_flipadst_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_dct_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_flipadst_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_identity_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_dct_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_identity_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_flipadst_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_adst_4x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_identity_4x4, lsx));
-
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_4x8, lsx));
-
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_adst_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_flipadst_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_dct_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_flipadst_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_flipadst_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_identity_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_dct_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_identity_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_flipadst_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_identity_8x4, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_adst_8x4, lsx));
-
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_adst_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_flipadst_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_dct_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_flipadst_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_adst_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_identity_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_identity_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_dct_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_flipadst_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_identity_8x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_flipadst_8x8, lsx));
-
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_8x16, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_8x16, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_8x16, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_8x16, lsx));
-
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_16x8, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_16x8, lsx));
+decl_itx17_fns( 4,  4, lsx);
+decl_itx16_fns( 4,  8, lsx);
+decl_itx16_fns( 4, 16, lsx);
+decl_itx16_fns( 8,  4, lsx);
+decl_itx16_fns( 8,  8, lsx);
+decl_itx16_fns( 8, 16, lsx);
+decl_itx2_fns ( 8, 32, lsx);
+decl_itx16_fns(16,  8, lsx);
+
+decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_16x4, lsx));
+decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_16x4, lsx));
+decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_16x4, lsx));
 
 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_16x16, lsx));
 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_16x16, lsx));
@@ -99,14 +50,23 @@ decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_16x16, lsx));
 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_16x16, lsx));
 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_dct_16x16, lsx));
 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_flipadst_16x16, lsx));
+decl_itx_fn(BF(dav1d_inv_txfm_add_adst_flipadst_16x16, lsx));
+decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_adst_16x16, lsx));
 
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_8x32, lsx));
-decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_32x32, lsx));
+decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_16x32, lsx));
+
+decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_32x8, lsx));
+
+decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_32x16, lsx));
 
 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_32x32, lsx));
 
+decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_64x32, lsx));
+
 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_64x64, lsx));
 
+decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_16x16, lasx));
+
 static ALWAYS_INLINE void itx_dsp_init_loongarch(Dav1dInvTxfmDSPContext *const c, int bpc) {
 #if BITDEPTH == 8
     const unsigned flags = dav1d_get_cpu_flags();
@@ -115,67 +75,20 @@ static ALWAYS_INLINE void itx_dsp_init_loongarch(Dav1dInvTxfmDSPContext *const c
 
     if (BITDEPTH != 8 ) return;
 
-    c->itxfm_add[TX_4X4][WHT_WHT]  = dav1d_inv_txfm_add_wht_wht_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][DCT_DCT]  = dav1d_inv_txfm_add_dct_dct_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][IDTX] = dav1d_inv_txfm_add_identity_identity_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][FLIPADST_DCT] = dav1d_inv_txfm_add_dct_flipadst_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][ADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_adst_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][FLIPADST_ADST] = dav1d_inv_txfm_add_adst_flipadst_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][DCT_FLIPADST] = dav1d_inv_txfm_add_flipadst_dct_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][FLIPADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_flipadst_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][H_DCT] = dav1d_inv_txfm_add_dct_identity_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][V_DCT] = dav1d_inv_txfm_add_identity_dct_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][H_FLIPADST] = dav1d_inv_txfm_add_flipadst_identity_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][V_FLIPADST] = dav1d_inv_txfm_add_identity_flipadst_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][V_ADST] = dav1d_inv_txfm_add_identity_adst_4x4_8bpc_lsx;
-    c->itxfm_add[TX_4X4][H_ADST] = dav1d_inv_txfm_add_adst_identity_4x4_8bpc_lsx;
-
-    c->itxfm_add[RTX_4X8][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_4x8_8bpc_lsx;
-
-    c->itxfm_add[RTX_8X4][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][IDTX] = dav1d_inv_txfm_add_identity_identity_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][ADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_adst_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][FLIPADST_ADST] = dav1d_inv_txfm_add_adst_flipadst_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][DCT_FLIPADST] = dav1d_inv_txfm_add_flipadst_dct_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][FLIPADST_DCT] = dav1d_inv_txfm_add_dct_flipadst_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][FLIPADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_flipadst_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][H_DCT] = dav1d_inv_txfm_add_dct_identity_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][V_DCT] = dav1d_inv_txfm_add_identity_dct_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][H_FLIPADST] = dav1d_inv_txfm_add_flipadst_identity_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][V_FLIPADST] = dav1d_inv_txfm_add_identity_flipadst_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][H_ADST] = dav1d_inv_txfm_add_adst_identity_8x4_8bpc_lsx;
-    c->itxfm_add[RTX_8X4][V_ADST] = dav1d_inv_txfm_add_identity_adst_8x4_8bpc_lsx;
-
-    c->itxfm_add[TX_8X8][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][IDTX] = dav1d_inv_txfm_add_identity_identity_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][ADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_adst_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][FLIPADST_ADST] = dav1d_inv_txfm_add_adst_flipadst_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][DCT_FLIPADST] = dav1d_inv_txfm_add_flipadst_dct_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][FLIPADST_DCT] = dav1d_inv_txfm_add_dct_flipadst_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][FLIPADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_flipadst_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][H_DCT] = dav1d_inv_txfm_add_dct_identity_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][V_DCT] = dav1d_inv_txfm_add_identity_dct_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][H_FLIPADST] = dav1d_inv_txfm_add_flipadst_identity_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][V_FLIPADST] = dav1d_inv_txfm_add_identity_flipadst_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][H_ADST] = dav1d_inv_txfm_add_adst_identity_8x8_8bpc_lsx;
-    c->itxfm_add[TX_8X8][V_ADST] = dav1d_inv_txfm_add_identity_adst_8x8_8bpc_lsx;
-
-    c->itxfm_add[RTX_8X16][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_8x16_8bpc_lsx;
-    c->itxfm_add[RTX_8X16][IDTX] = dav1d_inv_txfm_add_identity_identity_8x16_8bpc_lsx;
-    c->itxfm_add[RTX_8X16][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_8x16_8bpc_lsx;
-    c->itxfm_add[RTX_8X16][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_8x16_8bpc_lsx;
-
-    c->itxfm_add[RTX_16X8][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_16x8_8bpc_lsx;
-    c->itxfm_add[RTX_16X8][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_16x8_8bpc_lsx;
+    assign_itx17_fn( ,  4,  4, lsx);
+    assign_itx16_fn(R,  4,  8, lsx);
+    assign_itx16_fn(R,  4, 16, lsx);
+    assign_itx16_fn(R,  8,  4, lsx);
+    assign_itx16_fn( ,  8,  8, lsx);
+    assign_itx16_fn(R,  8, 16, lsx);
+    assign_itx2_fn (R,  8, 32, lsx);
+    assign_itx16_fn(R, 16,  8, lsx);
+    assign_itx1_fn (R, 64, 32, lsx);
+    assign_itx1_fn ( , 64, 64, lsx);
+
+    c->itxfm_add[RTX_16X4][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_16x4_8bpc_lsx;
+    c->itxfm_add[RTX_16X4][IDTX] = dav1d_inv_txfm_add_identity_identity_16x4_8bpc_lsx;
+    c->itxfm_add[RTX_16X4][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_16x4_8bpc_lsx;
 
     c->itxfm_add[TX_16X16][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_16x16_8bpc_lsx;
     c->itxfm_add[TX_16X16][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_16x16_8bpc_lsx;
@@ -183,12 +96,23 @@ static ALWAYS_INLINE void itx_dsp_init_loongarch(Dav1dInvTxfmDSPContext *const c
     c->itxfm_add[TX_16X16][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_16x16_8bpc_lsx;
     c->itxfm_add[TX_16X16][DCT_FLIPADST] = dav1d_inv_txfm_add_flipadst_dct_16x16_8bpc_lsx;
     c->itxfm_add[TX_16X16][FLIPADST_DCT] = dav1d_inv_txfm_add_dct_flipadst_16x16_8bpc_lsx;
+    c->itxfm_add[TX_16X16][FLIPADST_ADST] = dav1d_inv_txfm_add_adst_flipadst_16x16_8bpc_lsx;
+    c->itxfm_add[TX_16X16][ADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_adst_16x16_8bpc_lsx;
+
+    c->itxfm_add[RTX_16X32][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_16x32_8bpc_lsx;
 
-    c->itxfm_add[RTX_8X32][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_8x32_8bpc_lsx;
+    c->itxfm_add[RTX_32X8][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_32x8_8bpc_lsx;
+
+    c->itxfm_add[RTX_32X16][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_32x16_8bpc_lsx;
 
     c->itxfm_add[TX_32X32][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_32x32_8bpc_lsx;
 
-    c->itxfm_add[TX_64X64][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_64x64_8bpc_lsx;
+    if (!(flags & DAV1D_LOONGARCH_CPU_FLAG_LASX)) return;
+
+    if (BITDEPTH != 8 ) return;
+
+    c->itxfm_add[TX_16X16][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_16x16_8bpc_lasx;
+
 #endif
 }
 

src/loongarch/mc.h

@@ -43,6 +43,10 @@ decl_mask_fn(BF(dav1d_mask, lsx));
 decl_warp8x8_fn(BF(dav1d_warp_affine_8x8, lsx));
 decl_warp8x8t_fn(BF(dav1d_warp_affine_8x8t, lsx));
 decl_w_mask_fn(BF(dav1d_w_mask_420, lsx));
+decl_blend_fn(BF(dav1d_blend, lsx));
+decl_blend_dir_fn(BF(dav1d_blend_v, lsx));
+decl_blend_dir_fn(BF(dav1d_blend_h, lsx));
+decl_emu_edge_fn(BF(dav1d_emu_edge, lsx));
 
 decl_mc_fn(BF(dav1d_put_8tap_regular,          lsx));
 decl_mc_fn(BF(dav1d_put_8tap_regular_smooth,   lsx));
@@ -60,6 +64,17 @@ decl_mask_fn(BF(dav1d_mask, lasx));
 decl_warp8x8_fn(BF(dav1d_warp_affine_8x8, lasx));
 decl_warp8x8t_fn(BF(dav1d_warp_affine_8x8t, lasx));
 decl_w_mask_fn(BF(dav1d_w_mask_420, lasx));
+decl_blend_dir_fn(BF(dav1d_blend_h, lasx));
+
+decl_mct_fn(BF(dav1d_prep_8tap_regular,        lsx));
+decl_mct_fn(BF(dav1d_prep_8tap_regular_smooth, lsx));
+decl_mct_fn(BF(dav1d_prep_8tap_regular_sharp,  lsx));
+decl_mct_fn(BF(dav1d_prep_8tap_smooth,         lsx));
+decl_mct_fn(BF(dav1d_prep_8tap_smooth_regular, lsx));
+decl_mct_fn(BF(dav1d_prep_8tap_smooth_sharp,   lsx));
+decl_mct_fn(BF(dav1d_prep_8tap_sharp,          lsx));
+decl_mct_fn(BF(dav1d_prep_8tap_sharp_regular,  lsx));
+decl_mct_fn(BF(dav1d_prep_8tap_sharp_smooth,   lsx));
 
 decl_mct_fn(BF(dav1d_prep_8tap_regular,        lasx));
 decl_mct_fn(BF(dav1d_prep_8tap_regular_smooth, lasx));
@@ -83,6 +98,10 @@ static ALWAYS_INLINE void mc_dsp_init_loongarch(Dav1dMCDSPContext *const c) {
     c->warp8x8 = BF(dav1d_warp_affine_8x8, lsx);
     c->warp8x8t = BF(dav1d_warp_affine_8x8t, lsx);
     c->w_mask[2] = BF(dav1d_w_mask_420, lsx);
+    c->blend = BF(dav1d_blend, lsx);
+    c->blend_v = BF(dav1d_blend_v, lsx);
+    c->blend_h = BF(dav1d_blend_h, lsx);
+    c->emu_edge = BF(dav1d_emu_edge, lsx);
 
     init_mc_fn(FILTER_2D_8TAP_REGULAR,         8tap_regular,        lsx);
     init_mc_fn(FILTER_2D_8TAP_REGULAR_SMOOTH,  8tap_regular_smooth, lsx);
@@ -94,6 +113,16 @@ static ALWAYS_INLINE void mc_dsp_init_loongarch(Dav1dMCDSPContext *const c) {
     init_mc_fn(FILTER_2D_8TAP_SHARP_SMOOTH,    8tap_sharp_smooth,   lsx);
     init_mc_fn(FILTER_2D_8TAP_SHARP,           8tap_sharp,          lsx);
 
+    init_mct_fn(FILTER_2D_8TAP_REGULAR,        8tap_regular,        lsx);
+    init_mct_fn(FILTER_2D_8TAP_REGULAR_SMOOTH, 8tap_regular_smooth, lsx);
+    init_mct_fn(FILTER_2D_8TAP_REGULAR_SHARP,  8tap_regular_sharp,  lsx);
+    init_mct_fn(FILTER_2D_8TAP_SMOOTH_REGULAR, 8tap_smooth_regular, lsx);
+    init_mct_fn(FILTER_2D_8TAP_SMOOTH,         8tap_smooth,         lsx);
+    init_mct_fn(FILTER_2D_8TAP_SMOOTH_SHARP,   8tap_smooth_sharp,   lsx);
+    init_mct_fn(FILTER_2D_8TAP_SHARP_REGULAR,  8tap_sharp_regular,  lsx);
+    init_mct_fn(FILTER_2D_8TAP_SHARP_SMOOTH,   8tap_sharp_smooth,   lsx);
+    init_mct_fn(FILTER_2D_8TAP_SHARP,          8tap_sharp,          lsx);
+
     if (!(flags & DAV1D_LOONGARCH_CPU_FLAG_LASX)) return;
 
     c->avg = BF(dav1d_avg, lasx);
@@ -102,6 +131,7 @@ static ALWAYS_INLINE void mc_dsp_init_loongarch(Dav1dMCDSPContext *const c) {
     c->warp8x8 = BF(dav1d_warp_affine_8x8, lasx);
     c->warp8x8t = BF(dav1d_warp_affine_8x8t, lasx);
     c->w_mask[2] = BF(dav1d_w_mask_420, lasx);
+    c->blend_h = BF(dav1d_blend_h, lasx);
 
     init_mct_fn(FILTER_2D_8TAP_REGULAR,        8tap_regular,        lasx);
     init_mct_fn(FILTER_2D_8TAP_REGULAR_SMOOTH, 8tap_regular_smooth, lasx);

src/loongarch/msac.S

@@ -31,6 +31,12 @@ const min_prob
   .short 60, 56, 52, 48, 44, 40, 36, 32, 28, 24, 20, 16, 12, 8, 4, 0
 endconst
 
+const ph_0xff00
+.rept 8
+  .short 0xff00
+.endr
+endconst
+
 .macro decode_symbol_adapt w
     addi.d          sp,      sp,     -48
     addi.d          a4,      a0,      24
@@ -281,6 +287,82 @@ function msac_decode_bool_lsx
     move            a0,      t8
 endfunc
 
+function msac_decode_bool_equi_lsx
+    ld.w            t0,      a0,      24   // rng
+    ld.d            t1,      a0,      16   // dif
+    ld.w            a5,      a0,      28   // cnt
+    srli.w          t2,      t0,      8    // r >> 8
+    slli.w          t2,      t2,      7
+    addi.w          t2,      t2,      4    // v
+
+    slli.d          t3,      t2,      48   // vw
+    sltu            t4,      t1,      t3
+    move            t8,      t4            // ret
+    xori            t4,      t4,      1
+    maskeqz         t6,      t3,      t4   // if (ret) vw
+    sub.d           t6,      t1,      t6   // dif
+    slli.w          t5,      t2,      1
+    sub.w           t5,      t0,      t5   // r - 2v
+    maskeqz         t7,      t5,      t4   // if (ret) r - 2v
+    add.w           t5,      t2,      t7   // v(rng)
+
+    // renorm
+    clz.w           t4,      t5            // d
+    xori            t4,      t4,      16   // d
+    sll.d           t6,      t6,      t4
+    sll.w           t5,      t5,      t4
+    sub.w           t7,      a5,      t4   // cnt-d
+    st.w            t5,      a0,      24   // store rng
+    bgeu            a5,      t4,      9f
+
+    // refill
+    ld.d            t0,      a0,      0    // buf_pos
+    ld.d            t1,      a0,      8    // buf_end
+    addi.d          t2,      t0,      8
+    bltu            t1,      t2,      2f
+
+    ld.d            t3,      t0,      0    // next_bits
+    addi.w          t1,      t7,      -48  // shift_bits = cnt + 16 (- 64)
+    nor             t3,      t3,      t3
+    sub.w           t2,      zero,    t1
+    revb.d          t3,      t3            // next_bits = bswap(next_bits)
+    srli.w          t2,      t2,      3    // num_bytes_read
+    srl.d           t3,      t3,      t1   // next_bits >>= (shift_bits & 63)
+    b               3f
+1:
+    addi.w          t3,      t7,      -48
+    srl.d           t3,      t3,      t3   // pad with ones
+    b               4f
+2:
+    bgeu            t0,      t1,      1b
+    ld.d            t3,      t1,      -8   // next_bits
+    sub.w           t2,      t2,      t1
+    sub.w           t1,      t1,      t0   // num_bytes_left
+    slli.w          t2,      t2,      3
+    srl.d           t3,      t3,      t2
+    addi.w          t2,      t7,      -48
+    nor             t3,      t3,      t3
+    sub.w           t4,      zero,    t2
+    revb.d          t3,      t3
+    srli.w          t4,      t4,      3
+    srl.d           t3,      t3,      t2
+    sltu            t2,      t1,      t4
+    maskeqz         t1,      t1,      t2
+    masknez         t2,      t4,      t2
+    or              t2,      t2,      t1   // num_bytes_read
+3:
+    slli.w          t1,      t2,      3
+    add.d           t0,      t0,      t2
+    add.w           t7,      t7,      t1   // cnt += num_bits_read
+    st.d            t0,      a0,      0
+4:
+    or              t6,      t6,      t3   // dif |= next_bits
+9:
+    st.w            t7,      a0,      28   // store cnt
+    st.d            t6,      a0,      16   // store dif
+    move            a0,      t8
+endfunc
+
 function msac_decode_bool_adapt_lsx
     ld.hu           a3,      a1,      0    // cdf[0] /f
     ld.w            t0,      a0,      24   // rng
@@ -374,3 +456,162 @@ function msac_decode_bool_adapt_lsx
     st.d            t6,      a0,      16   // store dif
     move            a0,      t8
 endfunc
+
+.macro HI_TOK allow_update_cdf
+.\allow_update_cdf\()_hi_tok_lsx_start:
+.if \allow_update_cdf == 1
+    ld.hu        a4,    a1,    0x06 // cdf[3]
+.endif
+    vor.v        vr1,   vr0,   vr0
+    vsrli.h      vr1,   vr1,   0x06 // cdf[val] >> EC_PROB_SHIFT
+    vstelm.h     vr2,   sp,    0, 0 // -0x1a
+    vand.v       vr2,   vr2,   vr4  // (8 x rng) & 0xff00
+    vslli.h      vr1,   vr1,   0x07
+    vmuh.hu      vr1,   vr1,   vr2
+    vadd.h       vr1,   vr1,   vr5 // v += EC_MIN_PROB/* 4 */ * ((unsigned)n_symbols/* 3 */ - val);
+    vst          vr1,   sp,    0x02 // -0x18
+    vssub.hu     vr1,   vr1,   vr3 // v - c
+    vseqi.h      vr1,   vr1,   0
+.if \allow_update_cdf == 1
+    addi.d       t4,    a4,    0x50
+    srli.d       t4,    t4,    0x04
+    sltui        t7,    a4,    32
+    add.w        a4,    a4,    t7
+
+    vreplgr2vr.h vr7,   t4
+    vavgr.hu     vr9,   vr8,   vr1
+    vsub.h       vr9,   vr9,   vr0
+    vsub.h       vr0,   vr0,   vr1
+    vsra.h       vr9,   vr9,   vr7
+    vadd.h       vr0,   vr0,   vr9
+    vstelm.d     vr0,   a1,    0,  0
+    st.h         a4,    a1,    0x06
+.endif
+    vmsknz.b     vr7,   vr1
+    movfr2gr.s   t4,    f7
+    ctz.w        t4,    t4 // loop_times * 2
+    addi.d       t7,    t4,    2
+    ldx.hu       t6,    sp,    t4  // u
+    ldx.hu       t5,    sp,    t7  // v
+    addi.w       t3,    t3,    0x05
+    addi.w       t4,    t4,   -0x05 // if t4 == 3, continue
+    sub.w        t6,    t6,    t5   // u - v , rng for ctx_norm
+    slli.d       t5,    t5,    0x30 //  (ec_win)v << (EC_WIN_SIZE - 16)
+    sub.d        t1,    t1,    t5   //  s->dif - ((ec_win)v << (EC_WIN_SIZE - 16))
+    // Init ctx_norm  param
+    clz.w        t7,    t6
+    xori         t7,    t7,    0x1f
+    xori         t7,    t7,    0x0f //  d = 15 ^ (31 ^ clz(rng));
+    sll.d        t1,    t1,    t7   //  dif << d
+    sll.d        t6,    t6,    t7   //  rng << d
+    // update vr2 8 x rng
+    vreplgr2vr.h vr2,   t6
+    vreplvei.h   vr2,   vr2,   0
+    st.w         t6,    a0,    0x18 // store rng
+    move         t0,    t2
+    sub.w        t2,    t2,    t7   // cnt - d
+    bgeu         t0,    t7,    .\allow_update_cdf\()_hi_tok_lsx_ctx_norm_end     // if ((unsigned)cnt < (unsigned)d)  goto ctx_norm_end
+    // Step into ctx_fill
+    ld.d         t5,    a0,    0x00 // buf_pos
+    ld.d         t6,    a0,    0x08 // end_pos
+    addi.d       t7,    t5,    0x08 // buf_pos + 8
+    sub.d        t7,    t7,    t6   // (buf_pos + 8) - end_pos
+    blt          zero,  t7,    .\allow_update_cdf\()_hi_tok_lsx_ctx_refill_eob
+    // (end_pos - buf_pos) >= 8
+    ld.d         t6,    t5,    0x00 // load buf_pos[0]~buf_pos[7]
+    addi.w       t7,    t2,   -0x30 // cnt - 0x30
+    nor          t6,    t6,    t6   // not buf data
+    revb.d       t6,    t6          // Byte reversal
+    srl.d        t6,    t6,    t7   // Replace left shift with right shift
+    sub.w        t7,    zero,  t7   // neg
+    srli.w       t7,    t7,    0x03 // Loop times
+    or           t1,    t1,    t6   // dif |= (ec_win)(*buf_pos++ ^ 0xff) << c
+    b            .\allow_update_cdf\()_hi_tok_lsx_ctx_refill_end
+.\allow_update_cdf\()_hi_tok_lsx_ctx_refill_eob:
+    bge          t5,    t6,    .\allow_update_cdf\()_hi_tok_lsx_ctx_refill_one
+    // end_pos - buf_pos < 8 && buf_pos < end_pos
+    ld.d         t0,    t6,   -0x08
+    slli.d       t7,    t7,    0x03
+    srl.d        t6,    t0,    t7   // Retrieve the buf data and remove the excess data
+    addi.w       t7,    t2,   -0x30 // cnt - 0x30
+    nor          t6,    t6,    t6   // not
+    revb.d       t6,    t6          // Byte reversal
+    srl.d        t6,    t6,    t7   // Replace left shift with right shift
+    sub.w        t7,    zero,  t7   // neg
+    or           t1,    t1,    t6   // dif |= (ec_win)(*buf_pos++ ^ 0xff) << c
+    ld.d         t6,    a0,    0x08 // end_pos
+    srli.w       t7,    t7,    0x03 // Loop times
+    sub.d        t6,    t6,    t5   // end_pos - buf_pos
+    slt          t0,    t6,    t7
+    maskeqz      a3,    t6,    t0   // min(loop_times, end_pos - buf_pos)
+    masknez      t0,    t7,    t0
+    or           t7,    a3,    t0
+    b            .\allow_update_cdf\()_hi_tok_lsx_ctx_refill_end
+.\allow_update_cdf\()_hi_tok_lsx_ctx_refill_one:
+    // buf_pos >= end_pos
+    addi.w       t7,    t2,   -0x10
+    andi         t7,    t7,    0xf
+    nor          t0,    zero,  zero
+    srl.d        t0,    t0,    t7
+    or           t1,    t1,    t0 // dif |= ~(~(ec_win)0xff << c);
+    b            .\allow_update_cdf\()_hi_tok_lsx_ctx_norm_end
+.\allow_update_cdf\()_hi_tok_lsx_ctx_refill_end:
+    add.d        t5,    t5,    t7        // buf_pos + Loop_times
+    st.d         t5,    a0,    0x00      // Store buf_pos
+    alsl.w       t2,    t7,    t2,  0x03 // update cnt
+.\allow_update_cdf\()_hi_tok_lsx_ctx_norm_end:
+    srli.d       t7,    t1,    0x30
+    vreplgr2vr.h vr3,   t7        // broadcast the high 16 bits of dif
+    add.w        t3,    t4,    t3 // update control parameter
+    beqz         t3,    .\allow_update_cdf\()_hi_tok_lsx_end // control loop for at most 4 times.
+    blt          zero,  t4,    .\allow_update_cdf\()_hi_tok_lsx_start // tok_br == 3
+.\allow_update_cdf\()_hi_tok_lsx_end:
+    addi.d       t3,    t3,    0x1e
+    st.d         t1,    a0,    0x10 // store dif
+    st.w         t2,    a0,    0x1c // store cnt
+    srli.w       a0,    t3,    0x01 // tok
+    addi.d       sp,    sp,    0x1a
+.endm
+
+/**
+ * @param unsigned dav1d_msac_decode_hi_tok_c(MsacContext *const s, uint16_t *const cdf)
+ * * Reg Alloction
+ * * vr0: cdf;
+ * * vr1: temp;
+ * * vr2: rng;
+ * * vr3: dif;
+ * * vr4: const 0xff00ff00...ff00ff00;
+ * * vr5: const 0x0004080c;
+ * * vr6: const 0;
+ * * t0: allow_update_cdf, tmp;
+ * * t1: dif;
+ * * t2: cnt;
+ * * t3: 0xffffffe8, outermost control parameter;
+ * * t4: loop time
+ * * t5: v, buf_pos, temp;
+ * * t6: u, rng, end_pos, buf, temp;
+ * * t7: temp;
+ */
+function msac_decode_hi_tok_lsx
+    fld.d     f0,    a1,   0    // Load cdf[0]~cdf[3]
+    vldrepl.h vr2,   a0,   0x18 //  8 x rng, assert(rng <= 65535U), only the lower 16 bits are valid
+    vldrepl.h vr3,   a0,   0x16 // broadcast the high 16 bits of dif, c = s->dif >> (EC_WIN_SIZE - 16)
+    ld.w      t0,    a0,   0x20 // allow_update_cdf
+    la.local  t7,    ph_0xff00
+    vld       vr4,   t7,   0x00 // 0xff00ff00...ff00ff00
+    la.local  t7,    min_prob
+    vld       vr5,   t7,   12 * 2 // 0x0004080c
+    vxor.v    vr6,   vr6,  vr6    // const 0
+    ld.d      t1,    a0,   0x10   // dif
+    ld.w      t2,    a0,   0x1c   // cnt
+    orn       t3,    t3,   t3
+    srli.d    t3,    t3,   32
+    addi.d    t3,    t3,  -0x17 // 0xffffffe8
+    vseq.h    vr8,   vr8,  vr8
+    addi.d    sp,    sp,  -0x1a // alloc stack
+    beqz      t0,    .hi_tok_lsx_no_update_cdf
+    HI_TOK 1
+    jirl      zero,  ra,   0x0
+.hi_tok_lsx_no_update_cdf:
+    HI_TOK 0
+endfunc

src/loongarch/msac.h

@@ -36,11 +36,15 @@ unsigned dav1d_msac_decode_symbol_adapt16_lsx(MsacContext *s, uint16_t *cdf,
                                                size_t n_symbols);
 unsigned dav1d_msac_decode_bool_adapt_lsx(MsacContext *s, uint16_t *cdf);
 unsigned dav1d_msac_decode_bool_lsx(MsacContext *s, unsigned f);
+unsigned dav1d_msac_decode_bool_equi_lsx(MsacContext *s);
+unsigned dav1d_msac_decode_hi_tok_lsx(MsacContext *s, uint16_t *cdf);
 
 #define dav1d_msac_decode_symbol_adapt4  dav1d_msac_decode_symbol_adapt4_lsx
 #define dav1d_msac_decode_symbol_adapt8  dav1d_msac_decode_symbol_adapt8_lsx
 #define dav1d_msac_decode_symbol_adapt16 dav1d_msac_decode_symbol_adapt16_lsx
 #define dav1d_msac_decode_bool_adapt     dav1d_msac_decode_bool_adapt_lsx
 #define dav1d_msac_decode_bool           dav1d_msac_decode_bool_lsx
+#define dav1d_msac_decode_bool_equi      dav1d_msac_decode_bool_equi_lsx
+#define dav1d_msac_decode_hi_tok         dav1d_msac_decode_hi_tok_lsx
 
 #endif /* DAV1D_SRC_LOONGARCH_MSAC_H */

src/meson.build

@@ -239,6 +239,8 @@ if is_asm_enabled
         )}
 
         libdav1d_sources_asm = files(
+            'loongarch/cdef.S',
+            'loongarch/ipred.S',
             'loongarch/mc.S',
             'loongarch/loopfilter.S',
             'loongarch/looprestoration.S',

tests/checkasm/checkasm.h

@@ -334,6 +334,17 @@ void checkasm_stack_clobber(uint64_t clobber, ...);
                   7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0));\
     checkasm_set_signal_handler_state(0)
 #elif ARCH_RISCV
+#define declare_new(ret, ...)\
+    ret (*checked_call)(void *, int, int, int, int, int, int, int,\
+                        __VA_ARGS__, int, int, int, int, int, int, int, int,\
+                        int, int, int, int, int, int, int) =\
+    (void *)checkasm_checked_call;
+#define call_new(...)\
+    (checkasm_set_signal_handler_state(1),\
+     checked_call(func_new, 0, 0, 0, 0, 0, 0, 0, __VA_ARGS__,\
+                  7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0));\
+    checkasm_set_signal_handler_state(0)
+#elif ARCH_LOONGARCH
 #define declare_new(ret, ...)\
     ret (*checked_call)(void *, int, int, int, int, int, int, int,\
                         __VA_ARGS__, int, int, int, int, int, int, int, int,\

tests/checkasm/loongarch/checkasm.S

+/******************************************************************************
+ * Copyright © 2018, VideoLAN and dav1d authors
+ * Copyright © 2024, Loongson Technology Corporation Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+#define PRIVATE_PREFIX checkasm_
+
+#include "src/loongarch/loongson_asm.S"
+
+const register_init, align=4
+.quad 0x21f86d66c8ca00ce
+.quad 0x75b6ba21077c48ad
+.quad 0xed56bb2dcb3c7736
+.quad 0x8bda43d3fd1a7e06
+.quad 0xb64a9c9e5d318408
+.quad 0xdf9a54b303f1d3a3
+.quad 0x4a75479abd64e097
+.quad 0x249214109d5d1c88
+.quad 0x1a1b2550a612b48c
+.quad 0x79445c159ce79064
+.quad 0x2eed899d5a28ddcd
+.quad 0x86b2536fcd8cf636
+.quad 0xb0856806085e7943
+.quad 0x3f2bf84fc0fcca4e
+.quad 0xacbd382dcf5b8de2
+.quad 0xd229e1f5b281303f
+.quad 0x71aeaff20b095fd9
+.quad 0xab63e2e11fa38ed9
+endconst
+
+const error_message
+.asciz "failed to preserve register"
+endconst
+
+// max number of args used by any asm function.
+#define MAX_ARGS 15
+
+#define CLOBBER_STACK ((8*MAX_ARGS + 15) & ~15)
+
+// Fill dirty data at stack space
+function stack_clobber
+    move    t0,     sp
+    addi.d  t1,     zero,   CLOBBER_STACK
+1:
+    st.d    a0,     sp,     0x00
+    st.d    a1,     sp,    -0x08
+    addi.d  sp,     sp,    -0x10
+    addi.d  t1,     t1,    -0x10
+    blt     zero,   t1,     1b
+    move    sp,     t0
+endfunc
+
+#define ARG_STACK ((8*(MAX_ARGS - 8) + 15) & ~15)
+
+function checked_call
+    // Saved s0 - s8, fs0 - fs7
+    move    t4,     sp
+    addi.d  sp,     sp,     -136
+    st.d    s0,     sp,     0
+    st.d    s1,     sp,     8
+    st.d    s2,     sp,     16
+    st.d    s3,     sp,     24
+    st.d    s4,     sp,     32
+    st.d    s5,     sp,     40
+    st.d    s6,     sp,     48
+    st.d    s7,     sp,     56
+    st.d    s8,     sp,     64
+    fst.d   fs0,    sp,     72
+    fst.d   fs1,    sp,     80
+    fst.d   fs2,    sp,     88
+    fst.d   fs3,    sp,     96
+    fst.d   fs4,    sp,     104
+    fst.d   fs5,    sp,     112
+    fst.d   fs6,    sp,     120
+    fst.d   fs7,    sp,     128
+
+    la.local    t1,   register_init
+    ld.d    s0,     t1,     0
+    ld.d    s1,     t1,     8
+    ld.d    s2,     t1,     16
+    ld.d    s3,     t1,     24
+    ld.d    s4,     t1,     32
+    ld.d    s5,     t1,     40
+    ld.d    s6,     t1,     48
+    ld.d    s7,     t1,     56
+    ld.d    s8,     t1,     64
+    fld.d   fs0,    t1,     72
+    fld.d   fs1,    t1,     80
+    fld.d   fs2,    t1,     88
+    fld.d   fs3,    t1,     96
+    fld.d   fs4,    t1,     104
+    fld.d   fs5,    t1,     112
+    fld.d   fs6,    t1,     120
+    fld.d   fs7,    t1,     128
+
+    addi.d  sp,     sp,     -16
+    st.d    a1,     sp,     0 // ok
+    st.d    ra,     sp,     8 // Ret address
+
+    addi.d  sp,     sp,     -ARG_STACK
+
+    addi.d  t0,     zero,   8*8
+    xor     t1,     t1,     t1
+.rept MAX_ARGS - 8
+    // Skip the first 8 args, that are loaded into registers
+    ldx.d   t2,     t4,     t0
+    stx.d   t2,     sp,     t1
+    addi.d  t0,     t0,     8
+    addi.d  t1,     t1,     8
+.endr
+    move    t3,     a0  // Func
+    ld.d    a0,     t4,     0
+    ld.d    a1,     t4,     8
+    ld.d    a2,     t4,     16
+    ld.d    a3,     t4,     24
+    ld.d    a4,     t4,     32
+    ld.d    a5,     t4,     40
+    ld.d    a6,     t4,     48
+    ld.d    a7,     t4,     56
+
+    jirl    ra,     t3,     0
+
+    addi.d  sp,     sp,     ARG_STACK
+    ld.d    t2,     sp,     0 // ok
+    ld.d    ra,     sp,     8 // Ret address
+    addi.d  sp,     sp,     16
+
+    la.local    t1,   register_init
+    xor         t3,   t3,   t3
+
+.macro check_reg_gr reg1
+    ld.d    t0,     t1,      0
+    xor     t0,     $s\reg1, t0
+    or      t3,     t3,      t0
+    addi.d  t1,     t1,      8
+.endm
+    check_reg_gr 0
+    check_reg_gr 1
+    check_reg_gr 2
+    check_reg_gr 3
+    check_reg_gr 4
+    check_reg_gr 5
+    check_reg_gr 6
+    check_reg_gr 7
+    check_reg_gr 8
+
+.macro check_reg_fr reg1
+    ld.d        t0,     t1,     0
+    movfr2gr.d  t4,     $fs\reg1
+    xor         t0,     t0,     t4
+    or          t3,     t3,     t0
+    addi.d      t1,     t1,     8
+.endm
+    check_reg_fr 0
+    check_reg_fr 1
+    check_reg_fr 2
+    check_reg_fr 3
+    check_reg_fr 4
+    check_reg_fr 5
+    check_reg_fr 6
+    check_reg_fr 7
+
+    beqz    t3,     0f
+
+    st.d        zero,   t2,     0x00 // Set OK to 0
+    la.local    a0,     error_message
+    addi.d      sp,     sp,     -8
+    st.d        ra,     sp,     0
+    bl          puts
+    ld.d        ra,     sp,     0
+    addi.d      sp,     sp,     8
+0:
+    ld.d    s0,     sp,     0
+    ld.d    s1,     sp,     8
+    ld.d    s2,     sp,     16
+    ld.d    s3,     sp,     24
+    ld.d    s4,     sp,     32
+    ld.d    s5,     sp,     40
+    ld.d    s6,     sp,     48
+    ld.d    s7,     sp,     56
+    ld.d    s8,     sp,     64
+    fld.d   fs0,    sp,     72
+    fld.d   fs1,    sp,     80
+    fld.d   fs2,    sp,     88
+    fld.d   fs3,    sp,     96
+    fld.d   fs4,    sp,     104
+    fld.d   fs5,    sp,     112
+    fld.d   fs6,    sp,     120
+    fld.d   fs7,    sp,     128
+    addi.d  sp,     sp,     136
+endfunc

tests/checkasm/msac.c

@@ -280,6 +280,8 @@ void checkasm_check_msac(void) {
         c.decode_symbol_adapt16 = dav1d_msac_decode_symbol_adapt16_lsx;
         c.decode_bool_adapt     = dav1d_msac_decode_bool_adapt_lsx;
         c.decode_bool           = dav1d_msac_decode_bool_lsx;
+        c.decode_bool_equi      = dav1d_msac_decode_bool_equi_lsx;
+        c.decode_hi_tok         = dav1d_msac_decode_hi_tok_lsx;
     }
 #elif ARCH_X86 && HAVE_ASM
     if (dav1d_get_cpu_flags() & DAV1D_X86_CPU_FLAG_SSE2) {

tests/meson.build

@@ -73,6 +73,8 @@ if is_asm_enabled
         checkasm_asm_sources += files('checkasm/riscv/checkasm_64.S')
     elif host_machine.cpu_family().startswith('x86')
         checkasm_asm_objs += nasm_gen.process(files('checkasm/x86/checkasm.asm'))
+    elif host_machine.cpu_family().startswith('loongarch')
+        checkasm_asm_objs += files('checkasm/loongarch/checkasm.S')
     endif
 
     if use_gaspp