Fixes an integer overflow in inv_dct4_1d with
clusterfuzz-testcase-dav1d_fuzzer-5634807321591808 and in inv_adst16_1d
with clusterfuzz-testcase-dav1d_fuzzer-5761827623927808. Credits to oss-fuzz.

Fixes #220.

oss-fuzz can not handle shared libraries. Do not build it by default.

Link time optimization and '--wrap' seems to not work together.
Fixes #219.

Depends on posix_memalign and a linker supporting '--wrap' to wrap
arbitrary symbols.

Observed with
clusterfuzz-testcase-minimized-dav1d_fuzzer_mt-5700224002031616. Credits
to oss-fuzz.

Fixes #57, removes one rodata duplicate (vertical mv component is
identical to horizontal one), and removes memcpy() of rodata tables
to the source Dav1dThreadCdfContext for each frame where primary_ref
is PRIMARY_REF_NONE.

Prevents unnecessary returns from get_picture and fixes wrong return
value when a lower spatial level was dropped from output_picture()
(0 without a valid picture instead of -EAGAIN).

There are other checks present already that ensure the coded value remains within
the allowed range.

Fixes memory leaks and triggered asserts after random memory allocation
errors.

Reduces the aarch64 checkasm run time from 22s to 2.4s.

Janne Grunau authored 6 years ago and Henrik Gramner committed 6 years ago

Prevents unneeded downloading of the windows build artifacts.

Attempt to catch SIGFPE, SIGILL, and SIGSEGV and flag the current test as
failed instead of aborting abruptly.

Fixes #198.

Usage: --cpumask=0xf or --cpumask=ssse3 will select up to and
including SSSE3 (so SSE+SSE2+SSE3+SSSE3).

Liwei Wang authored 6 years ago and Henrik Gramner committed 6 years ago

Cycle times:
inv_txfm_add_4x4_adst_adst_0_8bpc_c: 445.9
inv_txfm_add_4x4_adst_adst_0_8bpc_ssse3: 23.7
inv_txfm_add_4x4_adst_adst_1_8bpc_c: 443.7
inv_txfm_add_4x4_adst_adst_1_8bpc_ssse3: 52.6
inv_txfm_add_4x4_adst_dct_0_8bpc_c: 474.5
inv_txfm_add_4x4_adst_dct_0_8bpc_ssse3: 23.9
inv_txfm_add_4x4_adst_dct_1_8bpc_c: 482.0
inv_txfm_add_4x4_adst_dct_1_8bpc_ssse3: 51.1
inv_txfm_add_4x4_adst_flipadst_0_8bpc_c: 587.2
inv_txfm_add_4x4_adst_flipadst_0_8bpc_ssse3: 24.0
inv_txfm_add_4x4_adst_flipadst_1_8bpc_c: 457.2
inv_txfm_add_4x4_adst_flipadst_1_8bpc_ssse3: 52.8
inv_txfm_add_4x4_adst_identity_0_8bpc_c: 412.4
inv_txfm_add_4x4_adst_identity_0_8bpc_ssse3: 43.3
inv_txfm_add_4x4_adst_identity_1_8bpc_c: 412.0
inv_txfm_add_4x4_adst_identity_1_8bpc_ssse3: 43.3
inv_txfm_add_4x4_dct_adst_0_8bpc_c: 467.4
inv_txfm_add_4x4_dct_adst_0_8bpc_ssse3: 23.2
inv_txfm_add_4x4_dct_adst_1_8bpc_c: 588.3
inv_txfm_add_4x4_dct_adst_1_8bpc_ssse3: 48.6
inv_txfm_add_4x4_dct_dct_0_8bpc_c: 611.5
inv_txfm_add_4x4_dct_dct_0_8bpc_ssse3: 23.1
inv_txfm_add_4x4_dct_dct_1_8bpc_c: 576.2
inv_txfm_add_4x4_dct_dct_1_8bpc_ssse3: 47.6
inv_txfm_add_4x4_dct_flipadst_0_8bpc_c: 479.5
inv_txfm_add_4x4_dct_flipadst_0_8bpc_ssse3: 23.4
inv_txfm_add_4x4_dct_flipadst_1_8bpc_c: 549.3
inv_txfm_add_4x4_dct_flipadst_1_8bpc_ssse3: 48.3
inv_txfm_add_4x4_dct_identity_0_8bpc_c: 576.9
inv_txfm_add_4x4_dct_identity_0_8bpc_ssse3: 25.4
inv_txfm_add_4x4_dct_identity_1_8bpc_c: 610.7
inv_txfm_add_4x4_dct_identity_1_8bpc_ssse3: 25.1
inv_txfm_add_4x4_flipadst_adst_0_8bpc_c: 532.8
inv_txfm_add_4x4_flipadst_adst_0_8bpc_ssse3: 23.8
inv_txfm_add_4x4_flipadst_adst_1_8bpc_c: 666.7
inv_txfm_add_4x4_flipadst_adst_1_8bpc_ssse3: 61.0
inv_txfm_add_4x4_flipadst_dct_0_8bpc_c: 539.6
inv_txfm_add_4x4_flipadst_dct_0_8bpc_ssse3: 23.8
inv_txfm_add_4x4_flipadst_dct_1_8bpc_c: 484.6
inv_txfm_add_4x4_flipadst_dct_1_8bpc_ssse3: 51.1
inv_txfm_add_4x4_flipadst_flipadst_0_8bpc_c: 503.1
inv_txfm_add_4x4_flipadst_flipadst_0_8bpc_ssse3: 23.9
inv_txfm_add_4x4_flipadst_flipadst_1_8bpc_c: 463.0
inv_txfm_add_4x4_flipadst_flipadst_1_8bpc_ssse3: 54.0
inv_txfm_add_4x4_flipadst_identity_0_8bpc_c: 719.9
inv_txfm_add_4x4_flipadst_identity_0_8bpc_ssse3: 43.0
inv_txfm_add_4x4_flipadst_identity_1_8bpc_c: 456.8
inv_txfm_add_4x4_flipadst_identity_1_8bpc_ssse3: 44.1
inv_txfm_add_4x4_identity_adst_0_8bpc_c: 422.8
inv_txfm_add_4x4_identity_adst_0_8bpc_ssse3: 42.4
inv_txfm_add_4x4_identity_adst_1_8bpc_c: 417.1
inv_txfm_add_4x4_identity_adst_1_8bpc_ssse3: 42.3
inv_txfm_add_4x4_identity_dct_0_8bpc_c: 435.4
inv_txfm_add_4x4_identity_dct_0_8bpc_ssse3: 25.7
inv_txfm_add_4x4_identity_dct_1_8bpc_c: 434.1
inv_txfm_add_4x4_identity_dct_1_8bpc_ssse3: 25.3
inv_txfm_add_4x4_identity_flipadst_0_8bpc_c: 528.1
inv_txfm_add_4x4_identity_flipadst_0_8bpc_ssse3: 40.9
inv_txfm_add_4x4_identity_flipadst_1_8bpc_c: 720.0
inv_txfm_add_4x4_identity_flipadst_1_8bpc_ssse3: 41.8
inv_txfm_add_4x4_identity_identity_0_8bpc_c: 383.2
inv_txfm_add_4x4_identity_identity_0_8bpc_ssse3: 28.3
inv_txfm_add_4x4_identity_identity_1_8bpc_c: 378.9
inv_txfm_add_4x4_identity_identity_1_8bpc_ssse3: 28.2
inv_txfm_add_4x4_wht_wht_0_8bpc_c: 271.5
inv_txfm_add_4x4_wht_wht_0_8bpc_ssse3: 34.0
inv_txfm_add_4x4_wht_wht_1_8bpc_c: 266.0
inv_txfm_add_4x4_wht_wht_1_8bpc_ssse3: 33.9

Xuefeng Jiang authored 6 years ago and Ronald S. Bultje committed 6 years ago

Cycle times:
intra_pred_h_w4_8bpc_c: 146.6
intra_pred_h_w4_8bpc_ssse3: 30.6
intra_pred_h_w8_8bpc_c: 236.3
intra_pred_h_w8_8bpc_ssse3: 42.2
intra_pred_h_w16_8bpc_c: 446.6
intra_pred_h_w16_8bpc_ssse3: 55.8
intra_pred_h_w32_8bpc_c: 688.2
intra_pred_h_w32_8bpc_ssse3: 85.9
intra_pred_h_w64_8bpc_c: 634.2
intra_pred_h_w64_8bpc_ssse3: 169.2

Coef was originally chosen to accomodate 12 bits/component with
4 extra precision intermediates + some under/overflow range, but
it turns out that 12 bits/component only uses 2 extra precision
intermediates, so we don't need coef.

Fixes #213.