1. 23 Aug, 2013 10 commits
  2. 05 Jul, 2013 1 commit
    • Henrik Gramner's avatar
      x86: Remove X264_CPU_SSE_MISALIGN functions · ff41804e
      Henrik Gramner authored
      Prevents a crash if the misaligned exception mask bit is cleared for some reason.
      
      Misaligned SSE functions are only used on AMD Phenom CPUs and the benefit is miniscule.
      They also require modifying the MXCSR control register and by removing those functions
      we can get rid of that complexity altogether.
      
      VEX-encoded instructions also supports unaligned memory operands. I tried adding AVX
      implementations of all removed functions but there were no performance improvements on
      Ivy Bridge. pixel_sad_x3 and pixel_sad_x4 had significant code size reductions though
      so I kept them and added some minor cosmetics fixes and tweaks.
      ff41804e
  3. 03 Jul, 2013 9 commits
  4. 28 May, 2013 1 commit
  5. 22 May, 2013 1 commit
  6. 20 May, 2013 17 commits
  7. 17 May, 2013 1 commit
    • Henrik Gramner's avatar
      x86: Don't use explicitly aligned versions of SAD on AVX CPUs · 33c35267
      Henrik Gramner authored
      On modern CPUs movdqu isn't slower than movdqa when used on aligned data and using the same code in both cases saves cache.
      
      This was already done for the high bit-depth AVX2 implementation but the aligned version still exists as dead code so remove that.
      33c35267