• Loren Merritt's avatar
    many changes to which asm functions are enabled on which cpus. · c0c0e1f4
    Loren Merritt authored
    with Phenom, 3dnow is no longer equivalent to "sse2 is slow", so make a new flag for that.
    some sse2 functions are useful only on Core2 and Phenom, so make a "sse2 is fast" flag for that.
    some ssse3 instructions didn't become useful until Penryn, so yet another flag.
    disable sse2 completely on Pentium M and Core1, because it's uniformly slower than mmx.
    enable some sse2 functions on Athlon64 that always were faster and we just didn't notice.
    remove mc_luma_sse3, because the only cpu that has lddqu (namely Pentium 4D) doesn't have "sse2 is fast".
    don't print mmx1, sse1, nor 3dnow in the detected cpuflags, since we don't really have any such functions. likewise don't print sse3 unless it's used (Pentium 4D).
    c0c0e1f4
cpu.h 1.96 KB