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Use write-combining for predictor checking and other tweaks.

Inlining trellis into the 4x4/8x8 trellis wrappers increases trellis speed by about 5-10% through constant propagation.

with Phenom, 3dnow is no longer equivalent to "sse2 is slow", so make a new flag for that.
some sse2 functions are useful only on Core2 and Phenom, so make a "sse2 is fast" flag for that.
some ssse3 instructions didn't become useful until Penryn, so yet another flag.
disable sse2 completely on Pentium M and Core1, because it's uniformly slower than mmx.
enable some sse2 functions on Athlon64 that always were faster and we just didn't notice.
remove mc_luma_sse3, because the only cpu that has lddqu (namely Pentium 4D) doesn't have "sse2 is fast".
don't print mmx1, sse1, nor 3dnow in the detected cpuflags, since we don't really have any such functions. likewise don't print sse3 unless it's used (Pentium 4D).

Cplxblur was originally intended to use a gaussian window, but in its current form did not.  This change provides a tiny improvement to 2pass ratecontrol.

Dramatically improves 1-pass VBV ratecontrol (especially CBR) and provides support for VBV in 2-pass mode.  This consists of a series of functions that attempts to find overflows and underflows in the VBV from the first-pass statsfile and fix them before encoding.
1-pass VBV code partially by Fiona Glaser.

Previously enabling noise reduction with threads had no effect.
Note that this is not an optimal solution; each thread still tracks noise reducation separately (unlike in single-threaded mode).

r852 introduced an assumption in deblock that the stack is aligned.

silence stderr in yasm version check.

this is the first non-runtime-detected use of mmxext, but it has to be inlined

(all other block types were already covered, but i16x16 cbp is special)

and a few other minor optimizations

it hasn't worked since probably some time in 2005, and won't ever be fixed unless someone steps up to maintain it.