1. 26 May, 2010 1 commit
    • Fiona Glaser's avatar
      Detect Atom CPU, enable appropriate asm functions · 57729402
      Fiona Glaser authored
      I'm not going to actually optimize for this pile of garbage unless someone pays me.
      But it can't hurt to at least enable the correct functions based on benchmarks.
      
      Also save some cache on Intel CPUs that don't need the decimate LUT due to having fast bsr/bsf.
      57729402
  2. 05 Apr, 2010 1 commit
    • Fiona Glaser's avatar
      Massive cosmetic and syntax cleanup · 58d2349d
      Fiona Glaser authored
      Convert all applicable loops to use C99 loop index syntax.
      Clean up most inconsistent syntax in ratecontrol.c, visualize, ppc, etc.
      Replace log(x)/log(2) constructs with log2, and similar with log10.
      Fix all -Wshadow violations.
      Fix visualize support.
      58d2349d
  3. 25 Feb, 2010 1 commit
  4. 17 Nov, 2009 1 commit
    • Fiona Glaser's avatar
      Faster weightp analysis · 63f71477
      Fiona Glaser authored
      Modify pixel_var slightly to return the necessary information and use it for weight analysis instead of sad/ssd.
      Various minor cosmetics.
      63f71477
  5. 24 Aug, 2009 1 commit
  6. 03 Jul, 2009 1 commit
    • Fiona Glaser's avatar
      Early termination for chroma encoding · 205a032c
      Fiona Glaser authored
      Faster chroma encoding by terminating early if heuristics indicate that the block will be DC-only.
      This works because the vast majority of inter chroma blocks have no coefficients at all, and those that do are almost always DC-only.
      Add two new helper DSP functions for this: dct_dc_8x8 and var2_8x8.  mmx/sse2/ssse3 versions of each.
      Early termination is disabled at very low QPs due to it not being useful there.
      Performance increase is ~1-2% without trellis, up to 5-6% with trellis=2.
      Increase is greater with lower bitrates.
      205a032c
  7. 31 Mar, 2009 1 commit
  8. 30 Mar, 2009 2 commits
  9. 17 Mar, 2009 1 commit
    • Fiona Glaser's avatar
      SSE2 zigzag_interleave · d25d50c9
      Fiona Glaser authored
      Replace PHADD with FastShuffle (more accurate naming).
      This flag represents asm functions that rely on fast SSE2 shuffle units, and thus are only faster on Phenom, Nehalem, and Penryn CPUs.
      d25d50c9
  10. 07 Mar, 2009 1 commit
    • Holger Lubitz's avatar
      Vastly faster SATD/SA8D/Hadamard_AC/SSD/DCT/IDCT · 54e38917
      Holger Lubitz authored
      Heavily optimized for Core 2 and Nehalem, but performance should improve on all modern x86 CPUs.
      16x16 SATD: +18% speed on K8(64bit), +22% on K10(32bit), +42% on Penryn(64bit), +44% on Nehalem(64bit), +50% on P4(32bit), +98% on Conroe(64bit)
      Similar performance boosts in SATD-like functions (SA8D, hadamard_ac) and somewhat less in DCT/IDCT/SSD.
      Overall performance boost is up to ~15% on 64-bit Conroe.
      54e38917
  11. 04 Mar, 2009 1 commit
    • Fiona Glaser's avatar
      Slightly faster 8x16 SAD on Penryn Core 2 · b77ea4db
      Fiona Glaser authored
      Same as MMX 8x16 cacheline SAD, but calls SSE2 8x16 SAD in non-cacheline case.
      Only Nehalem benefits from sizes smaller than 8x16, and Nehalem doesn't use cacheline functions, so no smaller versions are included.
      b77ea4db
  12. 11 Feb, 2009 1 commit
  13. 28 Jan, 2009 1 commit
  14. 31 Dec, 2008 1 commit
  15. 24 Dec, 2008 1 commit
    • Fiona Glaser's avatar
      Optimize variance asm + minor changes · 9fe6e5e6
      Fiona Glaser authored
      Remove SAD argument from var, not needed anymore.
      Speed up var asm a bit by eliminating psadbw and instead HADDWing at end.
      Eliminate all remaining warnings on gcc 3.4 on cygwin
      Port another minor optimization from lavc (pskip)
      9fe6e5e6
  16. 25 Nov, 2008 1 commit
    • Fiona Glaser's avatar
      Faster width4 SSD+SATD, SSE4 optimizations · 69e69197
      Fiona Glaser authored
      Do satd 4x8 by transposing the two blocks' positions and running satd 8x4.
      Use pinsrd (SSE4) for faster width4 SSD
      Globally replace movlhps with punpcklqdq (it seems to be faster on Conroe)
      Move mask_misalign declaration to cpu.h to avoid warning in encoder.c.
      These optimizations help on Nehalem, Phenom, and Penryn CPUs.
      69e69197
  17. 23 Nov, 2008 1 commit
    • Fiona Glaser's avatar
      Phenom CPU optimizations · 80ea99c0
      Fiona Glaser authored
      Faster hpel_filter by using unaligned loads instead of emulated PALIGNR
      Faster hpel_filter on 64-bit by using the 32-bit version (the cost of emulated PALIGNR is high enough that the savings from caching intermediate values is not worth it).
      Add support for misaligned_mask on Phenom: ~2% faster hpel_filter, ~4% faster width16 multisad, 7% faster width20 get_ref.
      Replace width12 mmx with width16 sse on Phenom and Nehalem: 32% faster width12 get_ref on Phenom.
      Merge cpu-32.asm and cpu-64.asm
      Thanks to Easy123 for contributing a Phenom box for a weekend so I could write these optimizations.
      80ea99c0
  18. 13 Nov, 2008 1 commit
  19. 10 Nov, 2008 1 commit
    • Fiona Glaser's avatar
      Various cosmetics and minor fixes · ae51235d
      Fiona Glaser authored
      Disable hadamard_ac sse2/ssse3 under stack_mod4
      Fix one MSVC compilation warning
      Fix compilation in debug mode in certain cases on x64
      Remove eval.c from MSVC project
      Fix crash when VBV is used in CQP mode
      Patches by MasterNobody
      ae51235d
  20. 15 Sep, 2008 1 commit
  21. 05 Sep, 2008 2 commits
  22. 16 Aug, 2008 1 commit
  23. 04 Jul, 2008 1 commit
    • Fiona Glaser's avatar
      Update file headers throughout x264 · bdbd4fe7
      Fiona Glaser authored
      Update "Authors" lists based on actual authorship; highest is most important
      Update copyright notices and remove old CVS tags from file headers
      Add file headers to GTK and other sections missing them
      Update FSF address
      Other header-related cosmetics
      bdbd4fe7
  24. 18 Jun, 2008 1 commit
  25. 08 Jun, 2008 2 commits
    • Loren Merritt's avatar
      many changes to which asm functions are enabled on which cpus. · c0c0e1f4
      Loren Merritt authored
      with Phenom, 3dnow is no longer equivalent to "sse2 is slow", so make a new flag for that.
      some sse2 functions are useful only on Core2 and Phenom, so make a "sse2 is fast" flag for that.
      some ssse3 instructions didn't become useful until Penryn, so yet another flag.
      disable sse2 completely on Pentium M and Core1, because it's uniformly slower than mmx.
      enable some sse2 functions on Athlon64 that always were faster and we just didn't notice.
      remove mc_luma_sse3, because the only cpu that has lddqu (namely Pentium 4D) doesn't have "sse2 is fast".
      don't print mmx1, sse1, nor 3dnow in the detected cpuflags, since we don't really have any such functions. likewise don't print sse3 unless it's used (Pentium 4D).
      c0c0e1f4
    • Loren Merritt's avatar
      enable ssse3 phadd satd on Penryn. · f9ad5ee2
      Loren Merritt authored
      f9ad5ee2
  26. 27 Apr, 2008 1 commit
  27. 20 Mar, 2008 1 commit
  28. 19 Mar, 2008 1 commit
  29. 16 Mar, 2008 2 commits
  30. 27 Jan, 2008 1 commit
  31. 06 Jan, 2008 1 commit
  32. 20 Nov, 2007 1 commit
  33. 18 Nov, 2007 1 commit
  34. 17 Nov, 2007 1 commit
  35. 24 Sep, 2007 1 commit
  36. 17 Jul, 2007 1 commit