cpu.c 11.6 KB
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/*****************************************************************************
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 * cpu.c: cpu detection
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 *****************************************************************************
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 * Copyright (C) 2003-2011 x264 project
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 *
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 * Authors: Loren Merritt <lorenm@u.washington.edu>
 *          Laurent Aimar <fenrir@via.ecp.fr>
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 *          Fiona Glaser <fiona@x264.com>
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02111, USA.
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 *
 * This program is also available under a commercial proprietary license.
 * For more information, contact us at licensing@x264.com.
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 *****************************************************************************/

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#define _GNU_SOURCE // for sched_getaffinity
#include "common.h"
#include "cpu.h"

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#if HAVE_PTHREAD && SYS_LINUX
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#include <sched.h>
#endif
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#if SYS_BEOS
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#include <kernel/OS.h>
#endif
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#if SYS_MACOSX || SYS_FREEBSD
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#include <sys/types.h>
#include <sys/sysctl.h>
#endif
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#if SYS_OPENBSD
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#include <sys/param.h>
#include <sys/sysctl.h>
#include <machine/cpu.h>
#endif
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const x264_cpu_name_t x264_cpu_names[] = {
    {"Altivec", X264_CPU_ALTIVEC},
//  {"MMX",     X264_CPU_MMX}, // we don't support asm on mmx1 cpus anymore
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    {"MMX2",    X264_CPU_MMX|X264_CPU_MMXEXT},
    {"MMXEXT",  X264_CPU_MMX|X264_CPU_MMXEXT},
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//  {"SSE",     X264_CPU_MMX|X264_CPU_MMXEXT|X264_CPU_SSE}, // there are no sse1 functions in x264
    {"SSE2Slow",X264_CPU_MMX|X264_CPU_MMXEXT|X264_CPU_SSE|X264_CPU_SSE2|X264_CPU_SSE2_IS_SLOW},
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    {"SSE2",    X264_CPU_MMX|X264_CPU_MMXEXT|X264_CPU_SSE|X264_CPU_SSE2},
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    {"SSE2Fast",X264_CPU_MMX|X264_CPU_MMXEXT|X264_CPU_SSE|X264_CPU_SSE2|X264_CPU_SSE2_IS_FAST},
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    {"SSE3",    X264_CPU_MMX|X264_CPU_MMXEXT|X264_CPU_SSE|X264_CPU_SSE2|X264_CPU_SSE3},
    {"SSSE3",   X264_CPU_MMX|X264_CPU_MMXEXT|X264_CPU_SSE|X264_CPU_SSE2|X264_CPU_SSE3|X264_CPU_SSSE3},
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    {"FastShuffle",   X264_CPU_MMX|X264_CPU_MMXEXT|X264_CPU_SSE|X264_CPU_SSE2|X264_CPU_SHUFFLE_IS_FAST},
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    {"SSE4.1",  X264_CPU_MMX|X264_CPU_MMXEXT|X264_CPU_SSE|X264_CPU_SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4},
    {"SSE4.2",  X264_CPU_MMX|X264_CPU_MMXEXT|X264_CPU_SSE|X264_CPU_SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4|X264_CPU_SSE42},
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    {"AVX", X264_CPU_AVX},
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    {"Cache32", X264_CPU_CACHELINE_32},
    {"Cache64", X264_CPU_CACHELINE_64},
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    {"SSEMisalign", X264_CPU_SSE_MISALIGN},
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    {"LZCNT", X264_CPU_LZCNT},
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    {"Slow_mod4_stack", X264_CPU_STACK_MOD4},
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    {"ARMv6", X264_CPU_ARMV6},
    {"NEON",  X264_CPU_NEON},
    {"Fast_NEON_MRC",  X264_CPU_FAST_NEON_MRC},
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    {"SlowCTZ", X264_CPU_SLOW_CTZ},
    {"SlowAtom", X264_CPU_SLOW_ATOM},
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    {"", 0},
};

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#if (ARCH_PPC && SYS_LINUX) || (ARCH_ARM && !HAVE_NEON)
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#include <signal.h>
#include <setjmp.h>
static sigjmp_buf jmpbuf;
static volatile sig_atomic_t canjump = 0;

static void sigill_handler( int sig )
{
    if( !canjump )
    {
        signal( sig, SIG_DFL );
        raise( sig );
    }

    canjump = 0;
    siglongjmp( jmpbuf, 1 );
}
#endif
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#if HAVE_MMX
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int x264_cpu_cpuid_test( void );
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void x264_cpu_cpuid( uint32_t op, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx );
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void x264_cpu_xgetbv( uint32_t op, uint32_t *eax, uint32_t *edx );
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uint32_t x264_cpu_detect( void )
{
    uint32_t cpu = 0;
    uint32_t eax, ebx, ecx, edx;
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    uint32_t vendor[4] = {0};
    int max_extended_cap;
    int cache;
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#if !ARCH_X86_64
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    if( !x264_cpu_cpuid_test() )
        return 0;
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#endif
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    x264_cpu_cpuid( 0, &eax, vendor+0, vendor+2, vendor+1 );
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    if( eax == 0 )
        return 0;

    x264_cpu_cpuid( 1, &eax, &ebx, &ecx, &edx );
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    if( edx&0x00800000 )
        cpu |= X264_CPU_MMX;
    else
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        return 0;
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    if( edx&0x02000000 )
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        cpu |= X264_CPU_MMXEXT|X264_CPU_SSE;
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    if( edx&0x04000000 )
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        cpu |= X264_CPU_SSE2;
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    if( ecx&0x00000001 )
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        cpu |= X264_CPU_SSE3;
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    if( ecx&0x00000200 )
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        cpu |= X264_CPU_SSSE3;
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    if( ecx&0x00080000 )
        cpu |= X264_CPU_SSE4;
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    if( ecx&0x00100000 )
        cpu |= X264_CPU_SSE42;
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    /* Check OXSAVE and AVX bits */
    if( (ecx&0x18000000) == 0x18000000 )
    {
        /* Check for OS support */
        x264_cpu_xgetbv( 0, &eax, &edx );
        if( (eax&0x6) == 0x6 )
            cpu |= X264_CPU_AVX;
    }
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    if( cpu & X264_CPU_SSSE3 )
        cpu |= X264_CPU_SSE2_IS_FAST;
    if( cpu & X264_CPU_SSE4 )
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        cpu |= X264_CPU_SHUFFLE_IS_FAST;
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    x264_cpu_cpuid( 0x80000000, &eax, &ebx, &ecx, &edx );
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    max_extended_cap = eax;

    if( !strcmp((char*)vendor, "AuthenticAMD") && max_extended_cap >= 0x80000001 )
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    {
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        cpu |= X264_CPU_SLOW_CTZ;
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        x264_cpu_cpuid( 0x80000001, &eax, &ebx, &ecx, &edx );
        if( edx&0x00400000 )
            cpu |= X264_CPU_MMXEXT;
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        if( cpu & X264_CPU_SSE2 )
        {
            if( ecx&0x00000040 ) /* SSE4a */
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            {
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                cpu |= X264_CPU_SSE2_IS_FAST;
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                cpu |= X264_CPU_LZCNT;
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                cpu |= X264_CPU_SHUFFLE_IS_FAST;
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                cpu &= ~X264_CPU_SLOW_CTZ;
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            }
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            else
                cpu |= X264_CPU_SSE2_IS_SLOW;
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            if( ecx&0x00000080 ) /* Misalign SSE */
            {
                cpu |= X264_CPU_SSE_MISALIGN;
                x264_cpu_mask_misalign_sse();
            }
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        }
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    }

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    if( !strcmp((char*)vendor, "GenuineIntel") )
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    {
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        x264_cpu_cpuid( 1, &eax, &ebx, &ecx, &edx );
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        int family = ((eax>>8)&0xf) + ((eax>>20)&0xff);
        int model  = ((eax>>4)&0xf) + ((eax>>12)&0xf0);
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        /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and 6/14 (core1 "yonah")
         * theoretically support sse2, but it's significantly slower than mmx for
         * almost all of x264's functions, so let's just pretend they don't. */
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        if( family == 6 && (model == 9 || model == 13 || model == 14) )
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        {
            cpu &= ~(X264_CPU_SSE2|X264_CPU_SSE3);
            assert(!(cpu&(X264_CPU_SSSE3|X264_CPU_SSE4)));
        }
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        /* Detect Atom CPU */
        if( family == 6 && model == 28 )
        {
            cpu |= X264_CPU_SLOW_ATOM;
            cpu |= X264_CPU_SLOW_CTZ;
        }
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    }
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    if( (!strcmp((char*)vendor, "GenuineIntel") || !strcmp((char*)vendor, "CyrixInstead")) && !(cpu&X264_CPU_SSE42))
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    {
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        /* cacheline size is specified in 3 places, any of which may be missing */
        x264_cpu_cpuid( 1, &eax, &ebx, &ecx, &edx );
        cache = (ebx&0xff00)>>5; // cflush size
        if( !cache && max_extended_cap >= 0x80000006 )
        {
            x264_cpu_cpuid( 0x80000006, &eax, &ebx, &ecx, &edx );
            cache = ecx&0xff; // cacheline size
        }
        if( !cache )
        {
            // Cache and TLB Information
            static const char cache32_ids[] = { 0x0a, 0x0c, 0x41, 0x42, 0x43, 0x44, 0x45, 0x82, 0x83, 0x84, 0x85, 0 };
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            static const char cache64_ids[] = { 0x22, 0x23, 0x25, 0x29, 0x2c, 0x46, 0x47, 0x49, 0x60, 0x66, 0x67,
                                                0x68, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7c, 0x7f, 0x86, 0x87, 0 };
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            uint32_t buf[4];
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            int max, i = 0;
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            do {
                x264_cpu_cpuid( 2, buf+0, buf+1, buf+2, buf+3 );
                max = buf[0]&0xff;
                buf[0] &= ~0xff;
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                for( int j = 0; j < 4; j++ )
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                    if( !(buf[j]>>31) )
                        while( buf[j] )
                        {
                            if( strchr( cache32_ids, buf[j]&0xff ) )
                                cache = 32;
                            if( strchr( cache64_ids, buf[j]&0xff ) )
                                cache = 64;
                            buf[j] >>= 8;
                        }
            } while( ++i < max );
        }
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        if( cache == 32 )
            cpu |= X264_CPU_CACHELINE_32;
        else if( cache == 64 )
            cpu |= X264_CPU_CACHELINE_64;
        else
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            x264_log( NULL, X264_LOG_WARNING, "unable to determine cacheline size\n" );
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    }
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#if BROKEN_STACK_ALIGNMENT
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    cpu |= X264_CPU_STACK_MOD4;
#endif

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    return cpu;
}

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#elif ARCH_PPC
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#if SYS_MACOSX || SYS_OPENBSD
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#include <sys/sysctl.h>
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uint32_t x264_cpu_detect( void )
{
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    /* Thank you VLC */
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    uint32_t cpu = 0;
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#if SYS_OPENBSD
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    int      selectors[2] = { CTL_MACHDEP, CPU_ALTIVEC };
#else
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    int      selectors[2] = { CTL_HW, HW_VECTORUNIT };
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#endif
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    int      has_altivec = 0;
    size_t   length = sizeof( has_altivec );
    int      error = sysctl( selectors, 2, &has_altivec, &length, NULL, 0 );

    if( error == 0 && has_altivec != 0 )
        cpu |= X264_CPU_ALTIVEC;

    return cpu;
}

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#elif SYS_LINUX
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uint32_t x264_cpu_detect( void )
{
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    static void (*oldsig)( int );
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    oldsig = signal( SIGILL, sigill_handler );
    if( sigsetjmp( jmpbuf, 1 ) )
    {
        signal( SIGILL, oldsig );
        return 0;
    }

    canjump = 1;
    asm volatile( "mtspr 256, %0\n\t"
                  "vand 0, 0, 0\n\t"
                  :
                  : "r"(-1) );
    canjump = 0;

    signal( SIGILL, oldsig );

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    return X264_CPU_ALTIVEC;
}
#endif

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#elif ARCH_ARM
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void x264_cpu_neon_test( void );
int x264_cpu_fast_neon_mrc_test( void );
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uint32_t x264_cpu_detect( void )
{
    int flags = 0;
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#if HAVE_ARMV6
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    flags |= X264_CPU_ARMV6;

    // don't do this hack if compiled with -mfpu=neon
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#if !HAVE_NEON
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    static void (* oldsig)( int );
    oldsig = signal( SIGILL, sigill_handler );
    if( sigsetjmp( jmpbuf, 1 ) )
    {
        signal( SIGILL, oldsig );
        return flags;
    }

    canjump = 1;
    x264_cpu_neon_test();
    canjump = 0;
    signal( SIGILL, oldsig );
#endif

    flags |= X264_CPU_NEON;

    // fast neon -> arm (Cortex-A9) detection relies on user access to the
    // cycle counter; this assumes ARMv7 performance counters.
    // NEON requires at least ARMv7, ARMv8 may require changes here, but
    // hopefully this hacky detection method will have been replaced by then.
    // Note that there is potential for a race condition if another program or
    // x264 instance disables or reinits the counters while x264 is using them,
    // which may result in incorrect detection and the counters stuck enabled.
    flags |= x264_cpu_fast_neon_mrc_test() ? X264_CPU_FAST_NEON_MRC : 0;
    // TODO: write dual issue test? currently it's A8 (dual issue) vs. A9 (fast mrc)
#endif
    return flags;
}

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#else

uint32_t x264_cpu_detect( void )
{
    return 0;
}

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#endif

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int x264_cpu_num_processors( void )
{
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#if !HAVE_THREAD
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    return 1;

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#elif defined(_WIN32)
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    return x264_pthread_num_processors_np();
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#elif SYS_LINUX
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    unsigned int bit;
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    int np;
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    cpu_set_t p_aff;
    memset( &p_aff, 0, sizeof(p_aff) );
    sched_getaffinity( 0, sizeof(p_aff), &p_aff );
    for( np = 0, bit = 0; bit < sizeof(p_aff); bit++ )
        np += (((uint8_t *)&p_aff)[bit / 8] >> (bit % 8)) & 1;
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    return np;

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#elif SYS_BEOS
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    system_info info;
    get_system_info( &info );
    return info.cpu_count;

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#elif SYS_MACOSX || SYS_FREEBSD || SYS_OPENBSD
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    int ncpu;
    size_t length = sizeof( ncpu );
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#if SYS_OPENBSD
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    int mib[2] = { CTL_HW, HW_NCPU };
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    if( sysctl(mib, 2, &ncpu, &length, NULL, 0) )
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#else
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    if( sysctlbyname("hw.ncpu", &ncpu, &length, NULL, 0) )
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#endif
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    {
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        ncpu = 1;
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    }
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    return ncpu;
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#else
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    return 1;
#endif
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}