- 04 Mar, 2019 2 commits
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François Cartegnie authored
--------------------- x86_64: ------------------------------------------ mct_8tap_regular_w4_0_8bpc_c: 115.6 mct_8tap_regular_w4_0_8bpc_ssse3: 13.1 mct_8tap_regular_w4_0_8bpc_avx2: 13.3 ------------------------------------------ mct_8tap_regular_w4_h_8bpc_c: 363.0 mct_8tap_regular_w4_h_8bpc_ssse3: 19.1 mct_8tap_regular_w4_h_8bpc_avx2: 16.5 ------------------------------------------ mct_8tap_regular_w4_hv_8bpc_c: 832.2 mct_8tap_regular_w4_hv_8bpc_ssse3: 113.4 mct_8tap_regular_w4_hv_8bpc_avx2: 53.1 ------------------------------------------ mct_8tap_regular_w4_v_8bpc_c: 488.5 mct_8tap_regular_w4_v_8bpc_ssse3: 38.9 mct_8tap_regular_w4_v_8bpc_avx2: 26.0 ------------------------------------------ mct_8tap_regular_w8_0_8bpc_c: 259.3 mct_8tap_regular_w8_0_8bpc_ssse3: 20.4 mct_8tap_regular_w8_0_8bpc_avx2: 18.0 ------------------------------------------ mct_8tap_regular_w8_h_8bpc_c: 1124.3 mct_8tap_regular_w8_h_8bpc_ssse3: 67.7 mct_8tap_regular_w8_h_8bpc_avx2: 43.3 ------------------------------------------ mct_8tap_regular_w8_hv_8bpc_c: 2155.0 mct_8tap_regular_w8_hv_8bpc_ssse3: 340.8 mct_8tap_regular_w8_hv_8bpc_avx2: 151.3 ------------------------------------------ mct_8tap_regular_w8_v_8bpc_c: 1195.4 mct_8tap_regular_w8_v_8bpc_ssse3: 72.4 mct_8tap_regular_w8_v_8bpc_avx2: 39.8 ------------------------------------------ mct_8tap_regular_w16_0_8bpc_c: 158.3 mct_8tap_regular_w16_0_8bpc_ssse3: 52.9 mct_8tap_regular_w16_0_8bpc_avx2: 30.2 ------------------------------------------ mct_8tap_regular_w16_h_8bpc_c: 4267.4 mct_8tap_regular_w16_h_8bpc_ssse3: 211.9 mct_8tap_regular_w16_h_8bpc_avx2: 121.4 ------------------------------------------ mct_8tap_regular_w16_hv_8bpc_c: 5430.9 mct_8tap_regular_w16_hv_8bpc_ssse3: 986.8 mct_8tap_regular_w16_hv_8bpc_avx2: 428.4 ------------------------------------------ mct_8tap_regular_w16_v_8bpc_c: 4604.2 mct_8tap_regular_w16_v_8bpc_ssse3: 199.1 mct_8tap_regular_w16_v_8bpc_avx2: 100.7 ------------------------------------------ mct_8tap_regular_w32_0_8bpc_c: 372.9 mct_8tap_regular_w32_0_8bpc_ssse3: 231.9 mct_8tap_regular_w32_0_8bpc_avx2: 99.7 ------------------------------------------ mct_8tap_regular_w32_h_8bpc_c: 15975.0 mct_8tap_regular_w32_h_8bpc_ssse3: 802.9 mct_8tap_regular_w32_h_8bpc_avx2: 468.5 ------------------------------------------ mct_8tap_regular_w32_hv_8bpc_c: 18555.5 mct_8tap_regular_w32_hv_8bpc_ssse3: 3673.5 mct_8tap_regular_w32_hv_8bpc_avx2: 1587.6 ------------------------------------------ mct_8tap_regular_w32_v_8bpc_c: 16632.4 mct_8tap_regular_w32_v_8bpc_ssse3: 743.5 mct_8tap_regular_w32_v_8bpc_avx2: 337.8 ------------------------------------------ mct_8tap_regular_w64_0_8bpc_c: 675.9 mct_8tap_regular_w64_0_8bpc_ssse3: 513.6 mct_8tap_regular_w64_0_8bpc_avx2: 285.4 ------------------------------------------ mct_8tap_regular_w64_h_8bpc_c: 37161.3 mct_8tap_regular_w64_h_8bpc_ssse3: 1929.7 mct_8tap_regular_w64_h_8bpc_avx2: 1138.1 ------------------------------------------ mct_8tap_regular_w64_hv_8bpc_c: 42434.0 mct_8tap_regular_w64_hv_8bpc_ssse3: 8822.1 mct_8tap_regular_w64_hv_8bpc_avx2: 3853.5 ------------------------------------------ mct_8tap_regular_w64_v_8bpc_c: 37969.1 mct_8tap_regular_w64_v_8bpc_ssse3: 1805.6 mct_8tap_regular_w64_v_8bpc_avx2: 826.1 ------------------------------------------ mct_8tap_regular_w128_0_8bpc_c: 1532.7 mct_8tap_regular_w128_0_8bpc_ssse3: 1397.7 mct_8tap_regular_w128_0_8bpc_avx2: 813.8 ------------------------------------------ mct_8tap_regular_w128_h_8bpc_c: 91204.3 mct_8tap_regular_w128_h_8bpc_ssse3: 4783.0 mct_8tap_regular_w128_h_8bpc_avx2: 2767.2 ------------------------------------------ mct_8tap_regular_w128_hv_8bpc_c: 102396.0 mct_8tap_regular_w128_hv_8bpc_ssse3: 22202.3 mct_8tap_regular_w128_hv_8bpc_avx2: 9637.2 ------------------------------------------ mct_8tap_regular_w128_v_8bpc_c: 92294.3 mct_8tap_regular_w128_v_8bpc_ssse3: 4952.8 mct_8tap_regular_w128_v_8bpc_avx2: 2370.1 ------------------------------------------ --------------------- x86_32: ------------------------------------------ mct_8tap_regular_w4_0_8bpc_c: 131.3 mct_8tap_regular_w4_0_8bpc_ssse3: 18.7 ------------------------------------------ mct_8tap_regular_w4_h_8bpc_c: 422.0 mct_8tap_regular_w4_h_8bpc_ssse3: 27.3 ------------------------------------------ mct_8tap_regular_w4_hv_8bpc_c: 1012.6 mct_8tap_regular_w4_hv_8bpc_ssse3: 123.6 ------------------------------------------ mct_8tap_regular_w4_v_8bpc_c: 589.6 mct_8tap_regular_w4_v_8bpc_ssse3: 48.9 ------------------------------------------ mct_8tap_regular_w8_0_8bpc_c: 278.5 mct_8tap_regular_w8_0_8bpc_ssse3: 26.3 ------------------------------------------ mct_8tap_regular_w8_h_8bpc_c: 1129.3 mct_8tap_regular_w8_h_8bpc_ssse3: 80.6 ------------------------------------------ mct_8tap_regular_w8_hv_8bpc_c: 2556.4 mct_8tap_regular_w8_hv_8bpc_ssse3: 354.6 ------------------------------------------ mct_8tap_regular_w8_v_8bpc_c: 1460.2 mct_8tap_regular_w8_v_8bpc_ssse3: 103.8 ------------------------------------------ mct_8tap_regular_w16_0_8bpc_c: 218.9 mct_8tap_regular_w16_0_8bpc_ssse3: 58.4 ------------------------------------------ mct_8tap_regular_w16_h_8bpc_c: 4471.8 mct_8tap_regular_w16_h_8bpc_ssse3: 237.2 ------------------------------------------ mct_8tap_regular_w16_hv_8bpc_c: 5570.5 mct_8tap_regular_w16_hv_8bpc_ssse3: 1044.1 ------------------------------------------ mct_8tap_regular_w16_v_8bpc_c: 4885.5 mct_8tap_regular_w16_v_8bpc_ssse3: 268.3 ------------------------------------------ mct_8tap_regular_w32_0_8bpc_c: 495.6 mct_8tap_regular_w32_0_8bpc_ssse3: 236.6 ------------------------------------------ mct_8tap_regular_w32_h_8bpc_c: 15903.5 mct_8tap_regular_w32_h_8bpc_ssse3: 872.5 ------------------------------------------ mct_8tap_regular_w32_hv_8bpc_c: 19402.2 mct_8tap_regular_w32_hv_8bpc_ssse3: 3832.8 ------------------------------------------ mct_8tap_regular_w32_v_8bpc_c: 17119.5 mct_8tap_regular_w32_v_8bpc_ssse3: 935.2 ------------------------------------------ mct_8tap_regular_w64_0_8bpc_c: 877.0 mct_8tap_regular_w64_0_8bpc_ssse3: 515.7 ------------------------------------------ mct_8tap_regular_w64_h_8bpc_c: 36832.1 mct_8tap_regular_w64_h_8bpc_ssse3: 2094.1 ------------------------------------------ mct_8tap_regular_w64_hv_8bpc_c: 43965.3 mct_8tap_regular_w64_hv_8bpc_ssse3: 9423.0 ------------------------------------------ mct_8tap_regular_w64_v_8bpc_c: 37041.2 mct_8tap_regular_w64_v_8bpc_ssse3: 2348.9 ------------------------------------------ mct_8tap_regular_w128_0_8bpc_c: 1929.9 mct_8tap_regular_w128_0_8bpc_ssse3: 1392.3 ------------------------------------------ mct_8tap_regular_w128_h_8bpc_c: 86022.5 mct_8tap_regular_w128_h_8bpc_ssse3: 5110.8 ------------------------------------------ mct_8tap_regular_w128_hv_8bpc_c: 105793.5 mct_8tap_regular_w128_hv_8bpc_ssse3: 23278.8 ------------------------------------------ mct_8tap_regular_w128_v_8bpc_c: 88223.5 mct_8tap_regular_w128_v_8bpc_ssse3: 7442.7 ------------------------------------------
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- 03 Mar, 2019 1 commit
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- 02 Mar, 2019 1 commit
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James Almer authored
VERSION_EXTRA is only needed in the binary FILEVERSION value, which consists of four 16 bit integers.
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- 01 Mar, 2019 10 commits
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Henrik Gramner authored
All known AVX2-capable CPU:s has BMI1 and BMI2, but apparently some x86 emulators can be configured to emulate esoteric combinations of instruction sets that doesn't correspond to any existing hardware.
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James Almer authored
The doxy for Dav1dPicAllocator.alloc_picture_callback() states it must be a negative errno value. Propagate it as well in picture_alloc_with_edges().
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James Almer authored
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Jean-Baptiste Kempf authored
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Jean-Baptiste Kempf authored
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Check the code for misspellings of 'dav1d'/'DAV1D' as 'david'/'DAVID'. This helps consistency and prevents bugs arising from these misspellings.
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Add an argument placeholder for the filmgrain option.
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Cycle times: inv_txfm_add_16x16_adst_adst_0_8bpc_c: 19643.8 inv_txfm_add_16x16_adst_adst_0_8bpc_ssse3: 870.0 inv_txfm_add_16x16_adst_adst_1_8bpc_c: 19611.7 inv_txfm_add_16x16_adst_adst_1_8bpc_ssse3: 870.3 inv_txfm_add_16x16_adst_adst_2_8bpc_c: 19554.2 inv_txfm_add_16x16_adst_adst_2_8bpc_ssse3: 869.9 inv_txfm_add_16x16_adst_dct_0_8bpc_c: 19499.2 inv_txfm_add_16x16_adst_dct_0_8bpc_ssse3: 761.1 inv_txfm_add_16x16_adst_dct_1_8bpc_c: 19819.1 inv_txfm_add_16x16_adst_dct_1_8bpc_ssse3: 760.9 inv_txfm_add_16x16_adst_dct_2_8bpc_c: 19684.5 inv_txfm_add_16x16_adst_dct_2_8bpc_ssse3: 761.4 inv_txfm_add_16x16_adst_flipadst_0_8bpc_c: 19309.3 inv_txfm_add_16x16_adst_flipadst_0_8bpc_ssse3: 877.2 inv_txfm_add_16x16_adst_flipadst_1_8bpc_c: 19374.3 inv_txfm_add_16x16_adst_flipadst_1_8bpc_ssse3: 876.8 inv_txfm_add_16x16_adst_flipadst_2_8bpc_c: 19548.6 inv_txfm_add_16x16_adst_flipadst_2_8bpc_ssse3: 879.4 inv_txfm_add_16x16_dct_adst_0_8bpc_c: 19715.3 inv_txfm_add_16x16_dct_adst_0_8bpc_ssse3: 757.6 inv_txfm_add_16x16_dct_adst_1_8bpc_c: 19586.6 inv_txfm_add_16x16_dct_adst_1_8bpc_ssse3: 756.8 inv_txfm_add_16x16_dct_adst_2_8bpc_c: 19447.3 inv_txfm_add_16x16_dct_adst_2_8bpc_ssse3: 757.2 inv_txfm_add_16x16_dct_dct_0_8bpc_c: 19188.0 inv_txfm_add_16x16_dct_dct_0_8bpc_ssse3: 64.3 inv_txfm_add_16x16_dct_dct_1_8bpc_c: 19230.1 inv_txfm_add_16x16_dct_dct_1_8bpc_ssse3: 649.1 inv_txfm_add_16x16_dct_dct_2_8bpc_c: 19276.7 inv_txfm_add_16x16_dct_dct_2_8bpc_ssse3: 649.5 inv_txfm_add_16x16_dct_flipadst_0_8bpc_c: 19967.8 inv_txfm_add_16x16_dct_flipadst_0_8bpc_ssse3: 761.1 inv_txfm_add_16x16_dct_flipadst_1_8bpc_c: 19665.7 inv_txfm_add_16x16_dct_flipadst_1_8bpc_ssse3: 761.0 inv_txfm_add_16x16_dct_flipadst_2_8bpc_c: 19766.2 inv_txfm_add_16x16_dct_flipadst_2_8bpc_ssse3: 760.6 inv_txfm_add_16x16_dct_identity_0_8bpc_c: 13874.5 inv_txfm_add_16x16_dct_identity_0_8bpc_ssse3: 97.3 inv_txfm_add_16x16_dct_identity_1_8bpc_c: 13931.8 inv_txfm_add_16x16_dct_identity_1_8bpc_ssse3: 76.3 inv_txfm_add_16x16_dct_identity_2_8bpc_c: 13801.5 inv_txfm_add_16x16_dct_identity_2_8bpc_ssse3: 454.6 inv_txfm_add_16x16_flipadst_adst_0_8bpc_c: 18900.6 inv_txfm_add_16x16_flipadst_adst_0_8bpc_ssse3: 884.6 inv_txfm_add_16x16_flipadst_adst_1_8bpc_c: 19180.2 inv_txfm_add_16x16_flipadst_adst_1_8bpc_ssse3: 886.7 inv_txfm_add_16x16_flipadst_adst_2_8bpc_c: 19320.8 inv_txfm_add_16x16_flipadst_adst_2_8bpc_ssse3: 884.6 inv_txfm_add_16x16_flipadst_dct_0_8bpc_c: 19399.7 inv_txfm_add_16x16_flipadst_dct_0_8bpc_ssse3: 775.0 inv_txfm_add_16x16_flipadst_dct_1_8bpc_c: 19345.0 inv_txfm_add_16x16_flipadst_dct_1_8bpc_ssse3: 774.6 inv_txfm_add_16x16_flipadst_dct_2_8bpc_c: 19426.2 inv_txfm_add_16x16_flipadst_dct_2_8bpc_ssse3: 775.6 inv_txfm_add_16x16_flipadst_flipadst_0_8bpc_c: 19457.6 inv_txfm_add_16x16_flipadst_flipadst_0_8bpc_ssse3: 887.8 inv_txfm_add_16x16_flipadst_flipadst_1_8bpc_c: 19413.8 inv_txfm_add_16x16_flipadst_flipadst_1_8bpc_ssse3: 885.3 inv_txfm_add_16x16_flipadst_flipadst_2_8bpc_c: 19425.6 inv_txfm_add_16x16_flipadst_flipadst_2_8bpc_ssse3: 886.3 inv_txfm_add_16x16_identity_dct_0_8bpc_c: 14150.7 inv_txfm_add_16x16_identity_dct_0_8bpc_ssse3: 104.3 inv_txfm_add_16x16_identity_dct_1_8bpc_c: 14041.5 inv_txfm_add_16x16_identity_dct_1_8bpc_ssse3: 104.2 inv_txfm_add_16x16_identity_dct_2_8bpc_c: 13917.7 inv_txfm_add_16x16_identity_dct_2_8bpc_ssse3: 459.7 inv_txfm_add_16x16_identity_identity_0_8bpc_c: 8761.7 inv_txfm_add_16x16_identity_identity_0_8bpc_ssse3: 263.3 inv_txfm_add_16x16_identity_identity_1_8bpc_c: 8669.5 inv_txfm_add_16x16_identity_identity_1_8bpc_ssse3: 263.4 inv_txfm_add_16x16_identity_identity_2_8bpc_c: 8282.1 inv_txfm_add_16x16_identity_identity_2_8bpc_ssse3: 263.3
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Ronald S. Bultje authored
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Matthias Dressel authored
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- 26 Feb, 2019 12 commits
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Janne Grunau authored
The operating_parameter_info is allowed to change in a single sequence. Reorder Dav1dSequenceHeader so the check for new sequence can still be done with memcmp and pffsetof.
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Victorien Le Couviour--Tuffet authored
AVX2 adaption --------------------- x86_64: ------------------------------------------ cdef_filter_4x4_8bpc_c: 1370.2 cdef_filter_4x4_8bpc_ssse3: 142.3 cdef_filter_4x4_8bpc_avx2: 106.7 ------------------------------------------ cdef_filter_4x8_8bpc_c: 2749.3 cdef_filter_4x8_8bpc_ssse3: 257.2 cdef_filter_4x8_8bpc_avx2: 178.8 ------------------------------------------ cdef_filter_8x8_8bpc_c: 5609.5 cdef_filter_8x8_8bpc_ssse3: 438.1 cdef_filter_8x8_8bpc_avx2: 250.6 ------------------------------------------ --------------------- x86_32: ------------------------------------------ cdef_filter_4x4_8bpc_c: 1548.7 cdef_filter_4x4_8bpc_ssse3: 179.8 ------------------------------------------ cdef_filter_4x8_8bpc_c: 3128.2 cdef_filter_4x8_8bpc_ssse3: 328.1 ------------------------------------------ cdef_filter_8x8_8bpc_c: 6454.5 cdef_filter_8x8_8bpc_ssse3: 584.4 ------------------------------------------
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Victorien Le Couviour--Tuffet authored
before: cdef_filter_4x4_8bpc_avx2: 110.4 after: cdef_filter_4x4_8bpc_avx2: 106.0 before: cdef_filter_4x8_8bpc_avx2: 188.3 after: cdef_filter_4x8_8bpc_avx2: 182.2 before: cdef_filter_8x8_8bpc_avx2: 276.7 after: cdef_filter_8x8_8bpc_avx2: 252.5 Credit to Gramner.
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Victorien Le Couviour--Tuffet authored
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Victorien Le Couviour--Tuffet authored
used for YUV 422 chroma blocks cdef_filter_4x8_8bpc_c: 2711.6 cdef_filter_4x8_8bpc_avx2: 189.1
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Victorien Le Couviour--Tuffet authored
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Victorien Le Couviour--Tuffet authored
- consistently use %3 instead of hardcoded value for tmp stride - also correct a comment
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Victorien Le Couviour--Tuffet authored
The chroma damping being set to luma damping - 1, we need to decrease the minimum damping value to ensure a proper clipping test for clip(0, d - log2(s)).
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Konstantin Pavlov authored
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Konstantin Pavlov authored
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Cycle times: inv_txfm_add_8x16_adst_adst_0_8bpc_c: 5063.0 inv_txfm_add_8x16_adst_adst_0_8bpc_ssse3: 406.8 inv_txfm_add_8x16_adst_adst_1_8bpc_c: 5051.2 inv_txfm_add_8x16_adst_adst_1_8bpc_ssse3: 407.3 inv_txfm_add_8x16_adst_adst_2_8bpc_c: 5065.4 inv_txfm_add_8x16_adst_adst_2_8bpc_ssse3: 407.9 inv_txfm_add_8x16_adst_dct_0_8bpc_c: 5201.1 inv_txfm_add_8x16_adst_dct_0_8bpc_ssse3: 354.8 inv_txfm_add_8x16_adst_dct_1_8bpc_c: 5214.8 inv_txfm_add_8x16_adst_dct_1_8bpc_ssse3: 354.8 inv_txfm_add_8x16_adst_dct_2_8bpc_c: 5225.0 inv_txfm_add_8x16_adst_dct_2_8bpc_ssse3: 355.1 inv_txfm_add_8x16_adst_flipadst_0_8bpc_c: 7135.9 inv_txfm_add_8x16_adst_flipadst_0_8bpc_ssse3: 409.7 inv_txfm_add_8x16_adst_flipadst_1_8bpc_c: 8354.4 inv_txfm_add_8x16_adst_flipadst_1_8bpc_ssse3: 409.2 inv_txfm_add_8x16_adst_flipadst_2_8bpc_c: 7198.7 inv_txfm_add_8x16_adst_flipadst_2_8bpc_ssse3: 409.7 inv_txfm_add_8x16_adst_identity_0_8bpc_c: 3936.5 inv_txfm_add_8x16_adst_identity_0_8bpc_ssse3: 262.0 inv_txfm_add_8x16_adst_identity_1_8bpc_c: 4617.8 inv_txfm_add_8x16_adst_identity_1_8bpc_ssse3: 261.4 inv_txfm_add_8x16_adst_identity_2_8bpc_c: 3895.1 inv_txfm_add_8x16_adst_identity_2_8bpc_ssse3: 262.1 inv_txfm_add_8x16_dct_adst_0_8bpc_c: 5203.9 inv_txfm_add_8x16_dct_adst_0_8bpc_ssse3: 355.1 inv_txfm_add_8x16_dct_adst_1_8bpc_c: 5200.8 inv_txfm_add_8x16_dct_adst_1_8bpc_ssse3: 355.4 inv_txfm_add_8x16_dct_adst_2_8bpc_c: 5208.2 inv_txfm_add_8x16_dct_adst_2_8bpc_ssse3: 355.1 inv_txfm_add_8x16_dct_dct_0_8bpc_c: 5270.8 inv_txfm_add_8x16_dct_dct_0_8bpc_ssse3: 57.0 inv_txfm_add_8x16_dct_dct_1_8bpc_c: 5280.9 inv_txfm_add_8x16_dct_dct_1_8bpc_ssse3: 303.2 inv_txfm_add_8x16_dct_dct_2_8bpc_c: 5275.9 inv_txfm_add_8x16_dct_dct_2_8bpc_ssse3: 302.4 inv_txfm_add_8x16_dct_flipadst_0_8bpc_c: 5374.4 inv_txfm_add_8x16_dct_flipadst_0_8bpc_ssse3: 356.5 inv_txfm_add_8x16_dct_flipadst_1_8bpc_c: 5449.9 inv_txfm_add_8x16_dct_flipadst_1_8bpc_ssse3: 356.8 inv_txfm_add_8x16_dct_flipadst_2_8bpc_c: 5446.9 inv_txfm_add_8x16_dct_flipadst_2_8bpc_ssse3: 356.7 inv_txfm_add_8x16_dct_identity_0_8bpc_c: 3883.4 inv_txfm_add_8x16_dct_identity_0_8bpc_ssse3: 76.1 inv_txfm_add_8x16_dct_identity_1_8bpc_c: 3892.3 inv_txfm_add_8x16_dct_identity_1_8bpc_ssse3: 76.1 inv_txfm_add_8x16_dct_identity_2_8bpc_c: 4027.1 inv_txfm_add_8x16_dct_identity_2_8bpc_ssse3: 209.9 inv_txfm_add_8x16_flipadst_adst_0_8bpc_c: 7387.5 inv_txfm_add_8x16_flipadst_adst_0_8bpc_ssse3: 408.9 inv_txfm_add_8x16_flipadst_adst_1_8bpc_c: 7298.8 inv_txfm_add_8x16_flipadst_adst_1_8bpc_ssse3: 408.8 inv_txfm_add_8x16_flipadst_adst_2_8bpc_c: 7397.2 inv_txfm_add_8x16_flipadst_adst_2_8bpc_ssse3: 408.9 inv_txfm_add_8x16_flipadst_dct_0_8bpc_c: 5250.4 inv_txfm_add_8x16_flipadst_dct_0_8bpc_ssse3: 355.3 inv_txfm_add_8x16_flipadst_dct_1_8bpc_c: 5263.9 inv_txfm_add_8x16_flipadst_dct_1_8bpc_ssse3: 355.4 inv_txfm_add_8x16_flipadst_dct_2_8bpc_c: 5259.0 inv_txfm_add_8x16_flipadst_dct_2_8bpc_ssse3: 356.3 inv_txfm_add_8x16_flipadst_flipadst_0_8bpc_c: 5448.4 inv_txfm_add_8x16_flipadst_flipadst_0_8bpc_ssse3: 410.2 inv_txfm_add_8x16_flipadst_flipadst_1_8bpc_c: 5402.6 inv_txfm_add_8x16_flipadst_flipadst_1_8bpc_ssse3: 410.8 inv_txfm_add_8x16_flipadst_flipadst_2_8bpc_c: 6479.7 inv_txfm_add_8x16_flipadst_flipadst_2_8bpc_ssse3: 409.8 inv_txfm_add_8x16_flipadst_identity_0_8bpc_c: 3828.9 inv_txfm_add_8x16_flipadst_identity_0_8bpc_ssse3: 262.7 inv_txfm_add_8x16_flipadst_identity_1_8bpc_c: 3884.5 inv_txfm_add_8x16_flipadst_identity_1_8bpc_ssse3: 262.0 inv_txfm_add_8x16_flipadst_identity_2_8bpc_c: 3809.2 inv_txfm_add_8x16_flipadst_identity_2_8bpc_ssse3: 262.9 inv_txfm_add_8x16_identity_adst_0_8bpc_c: 4294.5 inv_txfm_add_8x16_identity_adst_0_8bpc_ssse3: 268.8 inv_txfm_add_8x16_identity_adst_1_8bpc_c: 4955.4 inv_txfm_add_8x16_identity_adst_1_8bpc_ssse3: 269.1 inv_txfm_add_8x16_identity_adst_2_8bpc_c: 4166.4 inv_txfm_add_8x16_identity_adst_2_8bpc_ssse3: 269.9 inv_txfm_add_8x16_identity_dct_0_8bpc_c: 4012.3 inv_txfm_add_8x16_identity_dct_0_8bpc_ssse3: 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inv_txfm_add_16x8_dct_identity_1_8bpc_c: 4018.1 inv_txfm_add_16x8_dct_identity_1_8bpc_ssse3: 227.1 inv_txfm_add_16x8_dct_identity_2_8bpc_c: 3998.7 inv_txfm_add_16x8_dct_identity_2_8bpc_ssse3: 226.2 inv_txfm_add_16x8_flipadst_adst_0_8bpc_c: 5124.9 inv_txfm_add_16x8_flipadst_adst_0_8bpc_ssse3: 419.7 inv_txfm_add_16x8_flipadst_adst_1_8bpc_c: 5100.7 inv_txfm_add_16x8_flipadst_adst_1_8bpc_ssse3: 420.5 inv_txfm_add_16x8_flipadst_adst_2_8bpc_c: 5087.1 inv_txfm_add_16x8_flipadst_adst_2_8bpc_ssse3: 419.9 inv_txfm_add_16x8_flipadst_dct_0_8bpc_c: 5183.2 inv_txfm_add_16x8_flipadst_dct_0_8bpc_ssse3: 367.1 inv_txfm_add_16x8_flipadst_dct_1_8bpc_c: 5193.7 inv_txfm_add_16x8_flipadst_dct_1_8bpc_ssse3: 368.6 inv_txfm_add_16x8_flipadst_dct_2_8bpc_c: 5186.8 inv_txfm_add_16x8_flipadst_dct_2_8bpc_ssse3: 368.4 inv_txfm_add_16x8_flipadst_flipadst_0_8bpc_c: 5091.3 inv_txfm_add_16x8_flipadst_flipadst_0_8bpc_ssse3: 421.2 inv_txfm_add_16x8_flipadst_flipadst_1_8bpc_c: 5118.5 inv_txfm_add_16x8_flipadst_flipadst_1_8bpc_ssse3: 421.4 inv_txfm_add_16x8_flipadst_flipadst_2_8bpc_c: 5119.0 inv_txfm_add_16x8_flipadst_flipadst_2_8bpc_ssse3: 421.2 inv_txfm_add_16x8_flipadst_identity_0_8bpc_c: 3909.3 inv_txfm_add_16x8_flipadst_identity_0_8bpc_ssse3: 289.9 inv_txfm_add_16x8_flipadst_identity_1_8bpc_c: 3920.7 inv_txfm_add_16x8_flipadst_identity_1_8bpc_ssse3: 290.4 inv_txfm_add_16x8_flipadst_identity_2_8bpc_c: 3936.7 inv_txfm_add_16x8_flipadst_identity_2_8bpc_ssse3: 290.6 inv_txfm_add_16x8_identity_adst_0_8bpc_c: 3869.3 inv_txfm_add_16x8_identity_adst_0_8bpc_ssse3: 280.0 inv_txfm_add_16x8_identity_adst_1_8bpc_c: 3832.2 inv_txfm_add_16x8_identity_adst_1_8bpc_ssse3: 281.4 inv_txfm_add_16x8_identity_adst_2_8bpc_c: 3820.8 inv_txfm_add_16x8_identity_adst_2_8bpc_ssse3: 281.5 inv_txfm_add_16x8_identity_dct_0_8bpc_c: 3878.6 inv_txfm_add_16x8_identity_dct_0_8bpc_ssse3: 76.7 inv_txfm_add_16x8_identity_dct_1_8bpc_c: 3883.3 inv_txfm_add_16x8_identity_dct_1_8bpc_ssse3: 76.3 inv_txfm_add_16x8_identity_dct_2_8bpc_c: 3900.6 inv_txfm_add_16x8_identity_dct_2_8bpc_ssse3: 220.1 inv_txfm_add_16x8_identity_flipadst_0_8bpc_c: 3840.9 inv_txfm_add_16x8_identity_flipadst_0_8bpc_ssse3: 277.1 inv_txfm_add_16x8_identity_flipadst_1_8bpc_c: 3860.6 inv_txfm_add_16x8_identity_flipadst_1_8bpc_ssse3: 277.0 inv_txfm_add_16x8_identity_flipadst_2_8bpc_c: 3849.4 inv_txfm_add_16x8_identity_flipadst_2_8bpc_ssse3: 277.2 inv_txfm_add_16x8_identity_identity_0_8bpc_c: 2610.9 inv_txfm_add_16x8_identity_identity_0_8bpc_ssse3: 159.8 inv_txfm_add_16x8_identity_identity_1_8bpc_c: 2597.1 inv_txfm_add_16x8_identity_identity_1_8bpc_ssse3: 159.8 inv_txfm_add_16x8_identity_identity_2_8bpc_c: 2607.9 inv_txfm_add_16x8_identity_identity_2_8bpc_ssse3: 159.9
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- 25 Feb, 2019 1 commit
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Janne Grunau authored
The soname bump is required due to API changes since the 0.1.0 release. Fixes #247.
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- 22 Feb, 2019 1 commit
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Konstantin Pavlov authored
The push only happens under videolan namespace.
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- 21 Feb, 2019 4 commits
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Konstantin Pavlov authored
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Konstantin Pavlov authored
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Martin Storsjö authored
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Martin Storsjö authored
Remove the old "upstream" remote if set, to make sure it points to the right repo.
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- 20 Feb, 2019 6 commits
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Henrik Gramner authored
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Henrik Gramner authored
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Check all commits, not just the latest one, as a branch may consist of multiple commits. Exclude commits from upstream master (which may contain issues which we want to error out for on new commits).
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Ronald S. Bultje authored
Allows simplified SIMD function implementations that don't exactly respect picture boundaries when reading picture data. Fixes #251 and #250.
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Ronald S. Bultje authored
Allows aligned accesses to this array in SIMD. Fixes #246.
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Ronald S. Bultje authored
Fixes #252.
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- 19 Feb, 2019 2 commits
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James Almer authored
The references in the Dav1dContext may not necessarely apply to the picture being copied.
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Henrik Gramner authored
Eliminates segfault with clusterfuzz-testcase-minimized-dav1d_fuzzer-5697181166600192. Credit to OSS-Fuzz.
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