Commit 2f1ac5a8 authored by Laurent Aimar's avatar Laurent Aimar

Splitted SSE4 into SSE4.1, SSE4.2 and SSE4A.

parent 8c6b569c
......@@ -1488,15 +1488,35 @@ AS_IF([test "${enable_sse}" != "no"], [
AC_DEFINE(CAN_COMPILE_SSSE3, 1,
[Define to 1 if SSSE3 inline assembly is available.]) ])
# SSE4
AC_CACHE_CHECK([if $CC groks SSE4 inline assembly],
[ac_cv_sse4_inline],
# SSE4.1
AC_CACHE_CHECK([if $CC groks SSE4.1 inline assembly],
[ac_cv_sse4_1_inline],
[CFLAGS="${CFLAGS_save}"
AC_TRY_COMPILE(,[void *p;asm volatile("pmaxsb %%xmm1,%%xmm0"::"r"(p));],
ac_cv_sse4_inline=yes, ac_cv_sse4_inline=no)])
AS_IF([test "${ac_cv_sse4_inline}" != "no"], [
AC_DEFINE(CAN_COMPILE_SSE4, 1,
[Define to 1 if SSE4 inline assembly is available.]) ])
ac_cv_sse4_1_inline=yes, ac_cv_sse4_1_inline=no)])
AS_IF([test "${ac_cv_sse4_1_inline}" != "no"], [
AC_DEFINE(CAN_COMPILE_SSE4_1, 1,
[Define to 1 if SSE4_1 inline assembly is available.]) ])
# SSE4.2
AC_CACHE_CHECK([if $CC groks SSE4.2 inline assembly],
[ac_cv_sse4_2_inline],
[CFLAGS="${CFLAGS_save}"
AC_TRY_COMPILE(,[void *p;asm volatile("pcmpgtq %%xmm1,%%xmm0"::"r"(p));],
ac_cv_sse4_2_inline=yes, ac_cv_sse4_2_inline=no)])
AS_IF([test "${ac_cv_sse4_2_inline}" != "no"], [
AC_DEFINE(CAN_COMPILE_SSE4_2, 1,
[Define to 1 if SSE4_2 inline assembly is available.]) ])
# SSE4A
AC_CACHE_CHECK([if $CC groks SSE4A inline assembly],
[ac_cv_sse4a_inline],
[CFLAGS="${CFLAGS_save}"
AC_TRY_COMPILE(,[void *p;asm volatile("insertq %%xmm1,%%xmm0"::"r"(p));],
ac_cv_sse4a_inline=yes, ac_cv_sse4a_inline=no)])
AS_IF([test "${ac_cv_sse4a_inline}" != "no"], [
AC_DEFINE(CAN_COMPILE_SSE4A, 1,
[Define to 1 if SSE4A inline assembly is available.]) ])
])
AC_CACHE_CHECK([if $CC groks 3D Now! inline assembly],
......
......@@ -34,7 +34,9 @@
# define CPU_CAPABILITY_SSE2 (1<<7)
# define CPU_CAPABILITY_SSE3 (1<<8)
# define CPU_CAPABILITY_SSSE3 (1<<9)
# define CPU_CAPABILITY_SSE4 (1<<10)
# define CPU_CAPABILITY_SSE4_1 (1<<10)
# define CPU_CAPABILITY_SSE4_2 (1<<11)
# define CPU_CAPABILITY_SSE4A (1<<12)
# else
# define CPU_CAPABILITY_MMX (0)
# define CPU_CAPABILITY_3DNOW (0)
......@@ -43,7 +45,9 @@
# define CPU_CAPABILITY_SSE2 (0)
# define CPU_CAPABILITY_SSE3 (0)
# define CPU_CAPABILITY_SSSE3 (0)
# define CPU_CAPABILITY_SSE4 (0)
# define CPU_CAPABILITY_SSE4_1 (0)
# define CPU_CAPABILITY_SSE4_2 (0)
# define CPU_CAPABILITY_SSE4A (0)
# endif
# if defined (__ppc__) || defined (__ppc64__) || defined (__powerpc__)
......
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